NASA NTRS · 20210001472
This report focuses on second-order digital phase-locked loops (DPLLs) with uniformly sampled input, an amplitude-insenstive phase extractor and a conventional loop filter.
Thomas, J. B.. 1989-02-01. An analysis of digital phase-locked loops. https://ntrs.nasa.gov/citations/20210001472
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The baseline design and implementation of the digital baseband architecture for advanced deep space transponders is investigated and identified. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.
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