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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Graph Theory and IC Component Design Analysis

Graph analysis in large integrated circuit (IC) designs is an essential tool for verifying design logic and timing via dynamic timing analysis (DTA). IC designs resemble graphs with each logic gate as a vertex and the conductive connections between gates as edges. Using DTA digital statistical correlations, graph condensation, and graph partitioning, it is possible to identify high-entropy component centers and paths within an IC design. Identification of high-entropy component centers (HECC) enables focused DTA, effectively lowering the computational complexity of DTA on large integrated circuit graphs. In this paper, a devised methodology termed IC layout subgraph component center identification (CCI) is used to identify described. CCI lowers DTA computationally complexity by condensing IC graphs into reduced subgraphs in which dominant logic functions are verified.

42 ENGINEERING↗
DOE OSTI2023

Dislocation‐Induced Structural and Luminescence Degradation in InAs Quantum Dot Emitters on Silicon

This study probes the extent to which dislocations reduce carrier lifetimes and alter growth morphology and luminescence in InAs quantum dots (QD) grown on silicon. These heterostructures are key ingredients to achieving a highly reliable monolithically integrated light source on silicon necessary for photonic-integrated circuits. Around 20%–30% shorter carrier lifetimes are found at spatially resolved individual dislocations at room temperature using time-resolved cathodoluminescence spectroscopy, highlighting the strong nonradiative impact of dislocations even against the three-dimensional confinement of QDs. Beyond these direct effects of increased nonradiative recombination, it is found that misfit dislocations in the defect filter layers employed during III–V/Si growth alter the QD growth environment to induce a crosshatch-like variation in QD emission color and intensity when the filter layer is positioned sufficiently close to the QD emitter layer. Sessile threading dislocations generate even more egregious hillock defects that also reduce emission intensities by altering layer thicknesses, as measured by transmission electron microscopy and atom probe tomography. This work presents a more complete picture of the impacts of dislocations relevant to the development of light sources for scalable silicon photonic integrated circuits.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Development of a High-Rate Front-End ASIC for X-Ray Spectroscopy and Diffraction Applications

We developed a new front-end application-specific integrated circuit (ASIC) to upgrade the Maia X-ray microprobe. The ASIC instruments 32 configurable channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude, and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1-μs peaking time, and a temperature of 248 K, an electronic resolution of 13 and 10 e- rms was measured with and without a silicon drift detector (SDD) sensor, respectively. A spectral resolution of 170-eV full-width at half-maximum (FWHM) at 5.9 keV was obtained with an 55Fe source. The channel linearity was better than ± 1% with rate capabilities up to 40 kcps. The ASIC was fabricated in a commercial 250-nm process with a footprint of 6.3 mm × 3.9 mm and dissipates 167 mW of static power.

Vernon, Emerson↗
DOE OSTI2025

Tale of Two Domains: Cyber - Physical

As devices and systems continue to modernize and adopt integrated circuits, the use of cyber technology to deploy an application is the expectation. This deployment through cyber assets brings new cyber risk and cybersecurity is the practice of managing this risk. Cyber-risk is constantly changing due to the speed of technology advancement and the changing quality of the adversary. Cyber-Informed Engineering (CIE) mitigates cyber-risk through engineering controls where as the traditional practice of cybersecurity mitigates cyber-risk through cybersecurity controls. By clearly defining the cyber-physical boundary, engineering controls and cybersecurity controls can clearly demonstrate their complementary nature to provide layered defenses and successfully mitigate cyber-risk through independent controls. In this paper, a layered model of device decomposition of the the cyber-physical boundary is presented to provide clarity where engineering controls are used to reduce cyber-risk within the physics, functional materials, electronic, or integrated circuit layers and where cybersecurity controls are used to reduce cyber-risk within the machine code and application layers. By implementing both traditional cybersecurity controls and engineering controls, a more holistic approach to cybersecurity is achieved in protecting modern devices and systems, as well as a clear awareness in identifying, documenting, and authorizing the system’s cybersecurity protection scheme is achieved.

42 - ENGINEERING↗
DOE OSTI2025

PtCoO 2 for Scaled Interconnects

Copper (Cu) interconnects are an increasingly important bottleneck in integrated circuits due to energy consumption and latency caused by the notable increase in Cu resistivity as dimensions decrease, primarily due to electron scattering at surfaces. Herein, the potential of a directional conductor, PtCoO 2 , which has a low bulk resistivity and a distinctive anisotropic structure that mitigates electron surface scattering is showcased. Thin films of PtCoO 2 of various thicknesses are synthesized by molecular beam epitaxy (MBE) coupled with a postdeposition annealing process and the superior quality of PtCoO 2 films is demonstrated by multiple characterization techniques. The thickness‐dependent resistivity curve illustrates that PtCoO 2 significantly outperforms effective Cu (Cu with TaN barriers) and Ru in resistivity below 20.0 nm with a more than 6x reduction compared to effective Cu below 6.0 nm, having a value of only 6.32 μΩ cm at 3.3 nm. It is determined that grain boundary scattering can still be improved for even lower resistivities in this material system through a combination of experiments and theoretical simulations. PtCoO 2 is therefore a highly promising alternative material for future interconnect technologies promising lower resistivities, better stability, and significant improvements in energy efficiency and latency for advanced integrated circuits.

Li, Yansong [Department of Electrical Engineering ↗
DOE OSTI2022

Characterization of 128 × 128 MM-PAD-2.1 ASIC: a fast framing hard x-ray detector with high dynamic range

Here, we characterize a new x-ray Mixed-Mode Pixel Array Detector (MM-PAD-2.1) Application Specific Integrated Circuit (ASIC). Using an integrating pixel front-end with dynamic charge removal architecture, the MM-PAD-2.1 ASIC extends the maximum measurable x-ray signal (in 20 keV photon units) to > 10 7 x-rays/pixel/frame while maintaining a low read noise across the full dynamic range, all while imaging continuously at a frame rate of up to 10 kHz. The in-pixel dynamic charge removal mechanism prevents saturation of the input amplifier and proceeds in parallel with signal integration to achieve deadtime-less measurements with incident x-ray rates of > 10 10 x-rays/pixel/s. The ASIC format consists of 128 × 128 square pixels each 150 μm on a side and is designed to be 3-side buttable so large arrays can be effectively tiled. Here we use both laboratory x-ray sources and the Cornell High Energy Synchrotron Source (CHESS) to characterize two single ASIC prototype detectors for both low (single x-ray) and high incident flux detection. In the first detector the ASIC was solder bump-bonded to a 500 μm thick Si sensor for efficient detection of x-rays below 20 keV, whereas the second detector used a 750 μm thick CdTe sensor for x-rays above ~20 keV.

36 MATERIALS SCIENCE↗
DOE OSTI2026

IMPACT 2025-2026 Internship Poster

At Sandia National Laboratories, I developed a C++ program that converts printed circuit boards(PCB) and integrated circuits(IC) design files to be compatible for computed tomography (CT) simulations through Monte Carlo methods.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Electric-Field-Driven Localization of Molecular Nanowires in Wafer-Scale Nanogap Electrodes

As integrated circuits continue to scale toward the atomic limit, bottom-up processes, such as epitaxial growth, have come to feature prominently in their fabrication. At the same time, chemistry has developed highly tunable molecular semiconductors that can perform the functions of ultimately scaled circuit components. Hybrid techniques that integrate programmable structures comprising molecular components into devices however are sorely lacking. Here we demonstrate a wafer-scale process that directs the localization of a conductive polymer, M w = 20 kg mol –1 polyaniline, from dilute solutions into 50 nm vertical nanogap device architectures using electric-field-driven self-assembly. The resulting metal–polymer–metal junctions were characterized by electron microscopy, Raman spectroscopy and transport measurements demonstrating that our technique is highly selective, assembling conductive polymers only in electrically activated nanogaps. Our results represent a step toward scalable hybrid nanoelectronics that seamlessly integrate established lithographic top-down fabrication with bottom-up synthesized molecular functional circuit components.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2022

Integrable nonunitary quantum circuits

Here we show that the integrable Lindblad superoperators found recently can be used to build integrable nonunitary quantum circuits with two-site gates by demonstrating that the R(SIC) matrices are completely positive and trace preserving. Using the bond-site transformation, we obtain the corresponding integrable nonunitary quantum circuits with three-site gates. When restricted to the diagonals of the density matrix, these quantum models reduce to integrable classical cellular automata. This approach may pave the way for a systematic construction of circuits.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗
DOE OSTI2020

Direct laser writing of volumetric gradient index lenses and waveguides

Abstract Direct laser writing (DLW) has been shown to render 3D polymeric optical components, including lenses, beam expanders, and mirrors, with submicrometer precision. However, these printed structures are limited to the refractive index and dispersive properties of the photopolymer. Here, we present the subsurface controllable refractive index via beam exposure (SCRIBE) method, a lithographic approach that enables the tuning of the refractive index over a range of greater than 0.3 by performing DLW inside photoresist-filled nanoporous silicon and silica scaffolds. Adjusting the laser exposure during printing enables 3D submicron control of the polymer infilling and thus the refractive index and chromatic dispersion. Combining SCRIBE’s unprecedented index range and 3D writing accuracy has realized the world’s smallest (15 µm diameter) spherical Luneburg lens operating at visible wavelengths. SCRIBE’s ability to tune the chromatic dispersion alongside the refractive index was leveraged to render achromatic doublets in a single printing step, eliminating the need for multiple photoresins and writing sequences. SCRIBE also has the potential to form multicomponent optics by cascading optical elements within a scaffold. As a demonstration, stacked focusing structures that generate photonic nanojets were fabricated inside porous silicon. Finally, an all-pass ring resonator was coupled to a subsurface 3D waveguide. The measured quality factor of 4600 at 1550 nm suggests the possibility of compact photonic systems with optical interconnects that traverse multiple planes. SCRIBE is uniquely suited for constructing such photonic integrated circuits due to its ability to integrate multiple optical components, including lenses and waveguides, without additional printed supports.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Design principles of tandem cascade photoelectrochemical devices

Cascade photoelectrocatalysis (PEC) is a possible method to improve the selectivity of solar-driven CO 2 reduction (CO 2 R). This concept can be realized by coupling different CO 2 R catalysts to different subcells in a multijunction photovoltaic (PV) stack. Efficient implementation will require careful tuning of the photocurrents and design of the photovoltages provided by the subcells to the CO 2 R catalysts in such a way as to facilitate the target reaction. Here, we outline the design principles of the tandem PEC approach using two-step conversion of CO 2 to ethylene in aqueous electrolyte, via a CO intermediate, as a model system. To perform this reaction, the first coupled PV-catalyst component should provide 4 electrons to reduce 2 molecules of CO 2 to CO; the second component should provide 8 electrons to reduce 2 CO molecules to C 2 H 4 . Based on known CO 2 R catalysts, the overpotential required to produce CO can be less than that required to reduce it to ethylene, creating the opportunity for improved efficiency. Cascade PEC can be realized in a three-terminal tandem (3TT) configuration using III–V-semiconductor based subcells coupled to Au (produces CO intermediate) and Cu (converts CO to ethylene). The current to each catalyst can be controlled by the area of the subcell exposed to the electrolyte, and the photovoltage is determined by the materials selected and device configuration. Operating conditions are found by simulating the coupled system using the open-source circuit simulator SPICE (Simulation Program with Integrated Circuits Emphasis). We identify conditions under which a 3TT configuration can have a higher solar to chemical conversion efficiency compared to a two-terminal two-junction tandem (2T 2J) with the same absorbers and a Cu catalyst only. We also show that 3TT PEC devices can be less sensitive to variations in catalyst activity compared to 2T devices. Lastly, we discuss the applications of cascade PEC to CO 2 reduction, using different intermediates, and to other chemical networks.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2025

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗