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Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.
Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.
We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.
In order to achieve a high-efficiency high-density cryogenic instrumentation system, the power processing electronics should be placed in the cold environment along with the sensors and signal-processing electronics. The typical instrumentation system requires low voltage dc usually obtained from processing line frequency ac power. Switch-mode power conversion topologies such as forward, flyback, push-pull, and half-bridge are used for high-efficiency power processing using pulse-width modulation (PWM) or resonant control. This paper presents several PWM and multiresonant power control circuits, implemented using commercially available CMOS and BiCMOS integrated circuits, and their performance at liquid-nitrogen temperature (77 K) as compared to their room temperature (300 K) performance. The operation of integrated circuits at cryogenic temperatures results in an improved performance in terms of increased speed, reduced latch-up susceptibility, reduced leakage current, and reduced thermal noise. However, the switching noise increased at 77 K compared to 300 K. The power control circuits tested in the laboratory did successfully restart at 77 K.
A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.
Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.
A 12 bit successive approximation analog to digital converter that offers moderately high speed precision data conversion at a reasonable level of cost and complexity is studied. The ADCH10HT extends this capability over a temperature range of -55 to +200 C. No missing-code performance is maintained over the entire temperature range. The converter is completely self-contained with internal clock and +10 volt reference. The CMOS devices offer low power dissipation, so that the internal temperature of the hybrid circuit does not rise as much from self heating. In CMOS circuits, pn junction leakage currents are returned to the supplies so that the logic keeps working at temperatures up to 250 C.
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.
Si photonics has made rapid progress in research and commercialization in the past two decades. While it started with electronic–photonic integration on Si to overcome the interconnect bottleneck in data communications, Si photonics has now greatly expanded into optical sensing, light detection and ranging (LiDAR), optical computing, and microwave/RF photonics applications. From an applied physics point of view, this perspective discusses novel materials and integration schemes of active Si photonics devices for a broad range of applications in data communications, spectrally extended complementary metal–oxide–semiconductor (CMOS) image sensing, as well as 3D imaging for LiDAR systems. We also present a brief outlook of future synergy between Si photonic integrated circuits and Si CMOS image sensors toward ultrahigh capacity optical I/O, ultrafast imaging systems, and ultrahigh sensitivity lab-on-chip molecular biosensing.
This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.
Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.
Photodetector outputs digitized by circuitry on same integrated-circuit chip. Developmental special-purpose binary-output image sensor designed to capture up to 1,000 images per second, with resolution greater than 10 to the 6th power pixels per image. Lower-resolution but higher-frame-rate prototype of sensor contains 128 x 128 array of photodiodes on complementary metal oxide/semiconductor (CMOS) integrated-circuit chip. In application for which it is being developed, sensor used to examine helicopter oil to determine whether amount of metal and sand in oil sufficient to warrant replacement.
The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$ 60$\mu$m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps. Measurement results of in-pixel serial SAR ADC show DNL and INL of ~0. 44 LSB and 0.58 LBS respectively. A large area array of 20,000 SPROCKET2 ADC pixels (multiplexed 1:16 to 320,000 sensor pixels) is currently under test. By reading out data over a 10 Gbps optical link, this pixel design enables a frame rate of $\sim$ 4 kfps for large sensing areas with minimal sensing deadtime. In the highest gain mode, the pixelated ADC has an input-referred resolution of 10$\mu$V with a simulated power consumption of 50$\mu$W. The pixel operates with constant current draw to minimize power-rail crosstalk.
A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.
The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.
A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.
Simple circuit, compatible with CMOS logic, transfers digital signal between electrically isolated systems, without transistors, and minimum of discrete components.