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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗
DOE OSTI2023

The BiDFET Device and Its Impact on Converters

The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable D.C. link capacitors used in the popular Voltage-Source Inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems. The development of matrix converters has been hampered by the lack of availability of commercial bidirectional power switches with the ability to block high voltages in the first and third quadrants, carry on state current in both quadrants with low voltage drop, exhibit large forward-biased safe-operating-area (FBSOA), and low switching power losses. Consequently, many implementations have been tried in the past using discrete devices, as listed in Table I. Two implementations utilize commonly available asymmetric blocking IGBTs, while two cases make use of SiC power MOSFETs. They generally have a large parts count (4-6 individual switches) that occupies significant space in the converter where multiple bi-directional switches are required. They also have a high on-state voltage drop that degrades efficiency. As a result, one implementation utilizes symmetric blocking IGBT to achieve a low parts count (2), but its switching losses are unacceptably high.

42 ENGINEERING↗
DOE OSTI2023

Single-Phase Jet Impingement Cooling for a Power-Dense Silicon Carbide Power Module

The adoption of silicon carbide (SiC) devices in the electric vehicle (EV) industry is increasing due to their superior performance over silicon devices. SiC devices enable further miniaturization of EV inverters, increasing their power density, which results in thermal management challenges. Here in this paper, the limits of single-phase jet impingement cooling are explored for an automotive SiC power module. We propose embedding pin fins in the direct-bonded-copper (DBC) substrate of the power module package using laser powder bed fusion additive manufacturing. The thermalhydraulic performance of the DBC-embedded pin fins is compared against folded fins that are directly soldered to the DBC substrate. A heat conduction analysis was conducted on a SiC package to determine the target heat transfer coefficient (HTC) for the heat sink. A water-ethylene glycol (WEG) jet impingement on the proposed concepts was studied using unit-cell models to achieve the target HTC. The studied designs put emphasis on the reliability and manufacturability requirements of the automotive industry. The thermal performance of DBC-embedded pin fins outperformed the DBC-soldered folded fins. The performance of the DBC-embedded pin fins is benchmarked against WEG-based cooling systems of commercial EVs. With the proposed cooling solution, we have shown a pathway of reducing the specific thermal resistance by 75% compared to BMW i3 thermal management system without any penalty on pressure drop or parasitic power.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2020

Multi-Scale Thermal Analysis for Design of SiC-Based Medium Voltage Motor Drive: Preprint

This paper describes a multi-scale thermal analysis approach for the design of an air-cooled 1.7-kV SiC MOSFET-based medium-voltage variable-speed motor drive. The National Renewable Energy Laboratory supported the project objectives by providing thermal management design support to the project partner The Ohio State University (OSU). The scope of the models and limited resources required efficient and flexible thermal models to be developed. Two modeling techniques are described that significantly reduced model run time and enabled more complex models to be run faster while retaining needed accuracy. The first technique uses the effectiveness-NTU method to extract convection boundary conditions from a computational fluid dynamics (CFD) model that can be applied to a fast-running finite element analysis model. The second is a porous media technique that enables system-level CFD simulations that incorporate effects from heat exchangers (e.g., pin fin heat sinks) that run in a fraction of the time required for fully resolved CFD simulations. The multi-scale approach to the thermal analysis enabled fast and accurate simulation for the converter design ranging from the die level up to the full system with 36 submodules. The modeling results were validated against experimental data from system tests performed by OSU.

DIRECT ENERGY CONVERSION↗
DOE OSTI2020

Improving Heat Conduction of Insulated Metal Substrate with Thermal Pyrolytic Graphite Core for SiC Power Module Packaging

TPG-core IMS concept was jointly explored in this study. Integrating high thermally conductive TPG graphite core into IMS is expected to simultaneously achieve high thermal conductivity from TPG and electrical functionalities from IMS. Nearly 2x thermal conductivity and 30% weight saving was demonstrated on TPG-core IMS compared to conventional Cu-core IMS. Significant junction temperature reduction (11°C) in steady state and power cycling was revealed by the thermal analysis as the result of improved thermal spreading in plane and through the thickness. The study also proved the manufacturability and compatibility of this TPG-core IMS structure to the existing IMS production and power module assembling. Finally, the integration of TPG and IMS paves a new packaging route to increase heat load, improve reliability, simplify module design and reduce assembling cost and number of steps.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Graphite-Embedded High-Performance Insulated Metal Substrate for Wide-Bandgap Power Modules

Emerging wide-bandgap (WBG) semiconductor devices such as silicon carbide (SiC) metal–oxide semiconductor field-effect transistors (MOSFETs) and gallium nitride high-electron-mobility transistors can handle high power in reduced semiconductor areas better than conventional Si-based devices owing to superior material properties. With increased power loss density in a WBG-based converter and reduced die size in power modules, thermal management of power devices must be optimized for high performance. Here, we present a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite-embedded insulated metal substrate—IMSwTPG) designed for WBG power modules. Theoretical thermal performance analysis of graphite-embedded metal cores is presented, with design details for IMSwTPG with embedded graphite to replace a direct-bonded copper (DBC) substrate. The proposed IMSwTPG is compared with an aluminum nitride-based DBC substrate using finite-element thermal analysis for steady-state and transient thermal performance. The solutions’ thermal performances are compared under different coolant temperature and thermal loading conditions, and the proposed substrate's electrical performance is validated with static and dynamic characterization. Using graphite-embedded substrates, junction-to-case thermal resistance of SiC MOSFETs can be reduced up to 17%, and device current density can be increased by 10%, regardless of the thermal management strategy used to cool the substrate. Reduced transient thermal impedance of up to 40% of dies owing to increased heat capacity is validated in transient thermal simulations and experiments. The half-bridge power module's electrical performance is evaluated for on -state resistance, switching performance, and switching loss at three junction temperature conditions. The proposed substrate solution has minimal impact on conduction and switching performance of SiC MOSFETs.

42 ENGINEERING↗
DOE OSTI2023

Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability

To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (…2, 4, 2…) and (…2, 3, 2…) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device.

4H-SiC↗
DOE OSTI2023

A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities: Preprint

A wide range of utility applications require controllable switches with features such as high-voltage (HV) blocking and high-current carrying capacity especially at high pulse width modulation (PWM) frequency. Low and medium voltage utility applications such as motor drives and flexible AC transmission systems (FACTS) as well as solid state transformers (SST) could also benefit from a low-cost HV switching module. Wide band gap (WBG) semiconductors such as SiC and GaN MOSFETs are considered to be the present and next generation device choices, although they have their own limitations. For relatively HV applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low voltage regime. This manuscript proposes a new half bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in HV applications. Constructed from bare SiC dies, this half bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold and cooling, (3) integrated gate driver module with PWM over wi-fi to eliminate the need for low voltage signals, (4) wireless power transfer (WPT) enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state of health (SOH) estimator module onboard. The entire architecture has been designed and built at National Renewable Energy Laboratory (NREL), Golden, CO.

baseplate design↗
DOE OSTI2022

Nondestructive microstructural investigation of defects in 4H-SiC epilayers using a multiscale luminescence analysis approach

The development of metal oxide semiconductor field effect transistors (MOSFETs) utilizing epitaxially grown 4H-SiC has accelerated in recent years due to their favorable properties, including a high breakdown field, high saturated electron drift velocity, and good thermal conductivity. However, extended defects in epitaxial 4H-SiC can affect both device yields and operational lifetime. In this work, we demonstrate the importance of a multiscale luminescence characterization approach to studying nondestructively extended defects in epitaxial 4H-SiC semiconducting materials. Multiscale luminescence analysis reveals different aspects of excess charge carrier recombination behavior based on the scale of a particular measurement. Combining measurements of the same extended defect area at different scales tells us more about the essential nature of that defect and its microstructure. Here, we use photoluminescence imaging and cathodoluminescence spectrum imaging to investigate the recombination behavior of several different types of extended defects, including stacking faults, inclusions, and basal plane dislocations. A detailed understanding of the optoelectronic properties of extended defects in epitaxial SiC helps elucidate the microstructure of extended defects and can provide pathways to mitigate detrimental changes during device operation related to their evolution, such as the recombination enhanced dislocation glide effect that affects SiC-based MOSFETs.

3C-inclusion↗
DOE OSTI2020

Design, Analysis, Comparison, and Experimental Validation of Insulated Metal Substrates for High-Power Wide-Bandgap Power Modules

Direct bonded copper (DBC) substrates used in power modules have limited heat spreading and manufacturing capability due to ceramic properties and manufacturing technology. The ceramic and copper bonding is also subject to high mechanical stress due to coefficient of thermal expansion mismatch between the copper and the ceramic. For wide-bandgap (WBG) devices, it is of interest exploring new substrate technologies that can overcome some of the challenges of direct bonded copper substrates. In this technical paper, the design, analysis, and comparison of insulated metal substrates (IMSs) for high-power wide-bandgap semiconductor-based power modules are discussed. This paper starts with technical description and discussion of state-of-the-art DBC substrates with different ceramic insulators such as aluminum nitride (AlN), Al 2 O 3 , and Si 3 N 4 . Next, an introduction of IMSs and their material properties, and a design approach for SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET)-based power modules for high-power applications is provided. The influence of dielectric thickness on the power handling capability of the substrate are also discussed. The designed IMS and DBC substrates were characterized in terms of steady-state and transient thermal performance using finite element simulation. Finally, the performance of the IMS and DBC are validated in an experimental setup under different loading and cooling temperature conditions. We report the simulation and experimental results showed that the IMS can provide high steady-state thermal performance for high-power modules based on SiC MOSFETs. Furthermore, the IMS provided enhanced transient thermal performance, which provided a reduced junction temperature when the module is operated at low fundamental output frequencies in traction drive systems.

42 ENGINEERING↗
DOE OSTI2020

1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. Here, the BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

36 MATERIALS SCIENCE↗
DOE OSTI2022

7.2 kV Three-Port SiC Single-Stage Current-Source Solid-State Transformer With 90 kV Lightning Protection

This article proposes a multiport modular single-stage current-source solid-state transformer (SST) for applications like photovoltaic, energy storage integration, electric vehicle fast charging, data center, etc. The 7.2 kV 50 kVA current-source SST consists of five input-series output-parallel modules, each based on 3.3 kV SiC reverse-blocking MOSFET-plus-diode modules. The proposed SST has some unique features. First, compared to the voltage-source or matrix converter-based SSTs, the current-source SST has a unique advantage of single-stage isolated AC/DC or AC/AC conversion with an inductive DC link, but no medium-voltage (MV) AC experiments have been reported. This article for the first time demonstrates MV AC current-source SST up to 7.5 kV peak. Second, the multiport SST has a buffer port for active power decoupling (APD) or energy storage integration. The double-line-frequency power ripple from single-phase AC grid normally results in a large capacitor size in MV SSTs. The APD scheme is proposed in MV applications for the first time to enable a reduced DC link and the electrolytic capacitor-less SST with high reliability. Third, as a direct grid-connected converter without line-frequency transformer, insulation and protection are critical. A medium-frequency transformer design passes 55 kV basic-insulation level (BIL) and 60 kV high potential dielectrics withstand test with only 0.09% leakage inductance. Importantly, a lightning protection scheme is presented to protect the SST itself from 90 kV BIL impulse. Fourth, the proposed current-source SST topology is a modular soft-switching solid-state transformer (M-S4T) with full-range zero-voltage switching and controlled dv/dt for low electromagnetic interference. Furthermore, these concepts are verified in a three-port M-S4T prototype with forced oil cooling under single-module, stacked-module, steady-state, and dynamic operations.

14 SOLAR ENERGY↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2021

Instability Issue of Paralleled Dies in an SiC Power Module in Solid-State Circuit Breaker Applications

Paralleled dies in a power module could have instability issues during high current switching transients. Here, the instability is caused by the differential-mode oscillation among paralleled MOSFETs. Conventional analyses of paralleled MOSFETs’ stability are normally limited to a single operating point, which ignores the influences of the switching trajectory and nonlinear device parameters on stability. This article reveals that the switching trajectory can significantly influence parallel stability. The analysis is improved by solving eigenvalues of state-space modeling system matrices of all operating points that the switching trajectory goes through considering nonlinear device parameters. Higher voltage and current stresses result in greater real parts of complex eigenvalues, which explains why the paralleled MOSFETs are more unstable with higher voltage and current stresses. To improve stability in solid-state circuit breaker applications, we propose a method to manipulate the switching trajectory to avoid the unstable region where the conventional hard switching trajectory normally goes through. Experimental results show that the turn- off current capability can be increased from ~five times of rated current with the gate oscillation using the conventional turn- off trajectory to ~ten times of rated current without the gate oscillation using the optimal turn- off trajectory.

42 ENGINEERING↗
DOE OSTI2023

A Smart Silicon Carbide Power Module With Pulse Width Modulation Over Wi-Fi and Wireless Power Transfer-Enabled Gate Driver, Featuring Onboard State of Health Estimator and High-Voltage Scaling Capabilities

A wide range of utility applications require controllable switches with features such as high-voltage blocking and high-current carrying capacity, especially at high pulse width modulation (PWM) frequency. Low- and medium-voltage utility applications such as motor drives and flexible AC transmission systems as well as solid state transformers could also benefit from a low-cost high-voltage switching module. Wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) metal oxide semiconductor field effect transistors (MOSFETs) are considered to be the present and next-generation device choices, although they have limitations. For relatively high-voltage applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low-voltage regime. This manuscript proposes a new half-bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in high-voltage applications. Constructed from bare SiC dies, this half-bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold, and cooling, (3) integrated gate driver module with pulse width modulation (PWM) over wi-fi to eliminate the need for low-voltage signals, (4) wireless power transfer (WPT)-enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state-of-health (SOH) estimator module. The entire architecture has been designed and built at the National Renewable Energy Laboratory (NREL) in Golden, CO.

Ga2O3 devices↗
DOE OSTI2025

Rapid Prototyping Techniques for Organic Direct-Bonded-Copper Power Modules

Organic Direct-Bonded-Copper (ODBC) is a novel packaging technology for power modules which allows higher flexibility in layout design. In this work, a set of rapid prototyping techniques are developed for ODBC modules based on a polyimide dielectric material. These techniques enable fast and low-cost fabrication of modules with 3-Dimensional (3D) layout features. An example half-bridge (HB) silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) module is designed and prototyped using the proposed techniques aiming at ultra-low power loop inductance. Finite element analysis (FEA)-circuit co-simulations results and experimental results validate an approximately 0.71nH power loop inductance for the example module design.

36 MATERIALS SCIENCE↗