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108 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Expression of Interest in Contributions to the Electron-Ion Collider: Forward Silicon Vertex/Tracker Developments

The LANL EIC team would like to contribute to the EIC silicon vertex/tracking detector design, construction, commissioning and operation. Our primary focus is for a proposed forward silicon tracker with pseudorapidity coverage from 1 to 3.5 in the nucleon/nuclei beam going (forward) direction at IP-6 of the EIC. LANL LDRD is currently supporting this effort from FY20-FY22 with a funding of $5M. Meanwhile, we are open to collaborate on the other EIC detector sub-systems such as the central, backward silicon vertex/tracking detectors and/or a precision timing detector based on the LGAD technology.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

From ETROC to VTROC

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit, to reach 30-35ps per track with two detector layers. The ETROC2 is the first full size (16x16) prototype design and is fully compatible with the final chip specifications in terms of functionality. The ETROC2 has been extensively tested recently. In this talk, the testing results of the ETROC2 will be presented first, including performance study using charge injection, laser and beam, as well as TID testing and wafer probe testing to study the yield. In addition, future challenges of precision position and timing ASIC design will be discussed, based on what we have learned from the ETROC development, and how the challenges could be addressed in the VTROC, Vertically integrated Timing ReadOut chip (funded as SBIR phase 2) for precision position and timing detector R&D.

Liu, Ted↗
DOE OSTI2024

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade 520__ $$aThe Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

Gong, Datao↗
DOE OSTI2025

Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip

The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.

Fu, Tao [Unlisted, US]↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗
DOE OSTI2026

CMS Endcap Timing Layer: System Validation and Assembly

The High-Luminosity Large Hadron Collider (HL-LHC) will operate at unprecedented luminosities, resulting in up to 200 simultaneous interactions per bunch crossing. To mitigate the resulting pileup challenges, the CMS experiment is implementing the MIP Timing Detector (MTD), designed to provide precise timing information with a resolution of 30 – 40 picoseconds per track. The MTD consists of the Barrel Timing Layer (BTL) and the Endcap Timing Layer (ETL), each optimized for different regions of the detector. The ETL, comprising two double-sided disks, utilizes Low-Gain Avalanche Diode (LGAD) sensors coupled with the Endcap Timing Readout Chip (ETROC) to achieve high-precision timing measurements in the forward region. Significant progress has been made toward the realization of the ETL through extensive system-level validation of the ETROC readout chain and the development of scalable module assembly procedures. This presentation will provide a comprehensive overview of the ETL and highlight recent advances in system validation and module assembly, emphasizing their roles in ensuring the detector readiness for HL-LHC operation.

Lee, Dongyub [Kyungpook Natl. U.] (ORCID:000000034↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗
DOE OSTI2019

Studies of the FBK Low-Gain Avalanche Detectors for the CMS Endcap Timing Layer

• A detection efficiency of almost 100 percent observed throughout the surface of UFSD2 FBK 2x8 sensor • CFD Fraction between 30 and 50 percent yielded best time resolution measurements • Time resolution between 30 - 50 ps observed for the W5 FBK 3x1 mm2 sensors for different radiation fluences and bias voltages • A functional LGAD characterization system has been setup in the Testbeam Facility and Silicon Detector Facility at Fermilab

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 ps and 9.9 ps with and without the nonlinearity correction, respectively. The TDC block consumes 97 W at the hit occupancy of 1%. Over a temperature range from 23 C to 78 C and a power supply voltage range from 1.05 V to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation-tolerance specifications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2016

A new timing detector for the CT-PPS project

The CT-PPS detector will be installed close to the beam line on both sides of CMS, 200 m downstream the interaction point. This detector will measure forward scattered protons, allowing detailed studies of diffractive hadron physics and Central Exclusive Production. The main components of the CT-PPS detector are a silicon tracking system and a timing system. In this contribution we present the proposal of an innovative solution for the timing system, based on Ultra-Fast Silicon Detectors (UFSD). UFSD are a novel concept of silicon detectors potentially able to obtain the necessary time resolution (~20 ps on the proton arrival time). The use of UFSD has also other attractive features as its material budget is small and the pixel geometries can be tailored to the precise physics distribution of protons. UFSD prototypes for CT-PPS have been designed by CNM (Barcelona) and FBK (Trento): we will present the status of the sensor productions and of the low-noise front-end electronics currently under development and test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2018

Timing layers, 4- and 5-dimension tracking

The combination of precision space and time information in particle tracking, the so called 4D tracking, is being considered in the upgrade of the ATLAS, CMS and LHCb experiments at the High-Luminosity LHC, set to start data taking in 2024–2025. Regardless of the type of solution chosen, space–time tracking brings benefits to the performance of the detectors by reducing the background and sharpening the resolution; it improves tracking performances and simplifies tracks combinatorics. Space–time tracking also allows investigating new physics channels, for example it opens up the possibilities of new searches in long-living particles by measuring accurately the time of flight between the production and the decay vertexes. The foreseen applications of 4D tracking in experiments with very high acquisition rates, for example at HL-LHC, add one more dimension to the problem, increasing dramatically the complexity of the read-out system and that of the whole detector design: we call 5D tracking the application of 4D tracking in high rate environments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

State-of-the-art and evolution of UFSD sensors design at FBK

Over the past few years, there has been growing interest in the development of silicon sensors able to simultaneously measure accurately the time of passage and the position of impinging charged particles. In this contribution, a review of the progresses in the design of UFSD (Ultra-Fast Silicon Detectors) sensors, manufactured at the FBK (Fondazione Bruno Kessler) Foundry, aiming at tracking charged particles in 4 dimensions, is presented. The state-of-the-art UFSD sensors, with excellent timing capability, are planned to be used in both ATLAS and CMS experiments detector upgrade, in order to reduce the background due to the presence of overlapping events in the same bunch crossing. The latest results on sensors characterization including time resolution, radiation resistance and uniformity of the response are here summarized, pointing out the interplay between the design of the gain layer and the UFSD performances. The research is now focusing on the maximization of the sensor fill factor, to be able to reduce the pixel size, exploring the implementation of shallow trenches for the pixel isolation and the development of resistive AC-coupled UFSD sensors. In conclusion, a brief review on research paths tailored for detection of low energy X-rays or for low material budget applications is given.

47 OTHER INSTRUMENTATION↗