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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Integrated-Circuit Pseudorandom-Number Generator

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

Steelman, James E.↗
NASA NTRS1992

The flip flop nozzle extended to supersonic flows

An experiment studying a fluidically oscillated rectangular jet flow was conducted. The Mach number was varied over a range from low subsonic to supersonic. Unsteady velocity and pressure measurements were made using hot wires and piezoresistive pressure transducers. In addition smoke flow visualization using high speed photography was used to document the oscillation of the jet. For the subsonic flip-flop jet it was found that the apparent time-mean widening of the jet was not accompanied by an increase in mass flux. It was found that it is possible to extend the operation of these devices to supersonic flows. Most of the measurements were made for a fixed nozzle geometry for which the oscillations ceased at a fully expanded Mach number of 1.58. By varying the nozzle geometry this limitation was overcome and operation was extended to Mach 1.8. The streamwise velocity perturbation levels produced by this device were much higher than the perturbation levels that could be produced using conventional excitation sources such as acoustic drivers. In view of this ability to produce high amplitudes, the potential for using small scale fluidically oscillated jet as an unsteady excitation source for the control of shear flows in full scale practical applications seems promising.

Raman, Ganesh↗
NASA NTRS1993

Postirradiation Effects In Integrated Circuits

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Shaw, David C.↗
NASA NTRS1992

BETA: Behavioral testability analyzer and its application to high-level test generation and synthesis for testability

In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach call Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits.

Chen, Chung-Hsing↗
NASA NTRS1992

Low power SEU immune CMOS memory circuits

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.↗
NASA NTRS1994

Three-dimensional hydrodynamic Bondi-Hoyle accretion. 2: Homogeneous medium at Mach 3 with gamma = 5/3

We investigate the hydrodynamics of three-dimensional classical Bondi-Hoyle accretion. Totally absorbing spheres of varying sizes (from 10 down to 0.01 accretion radii) move at Mach 3 relative to a homogeneous and slightly perturbed medium, which is taken to be an ideal gas (gamma = 5/3). To accommodate the long-range gravitational forces, the extent of the computational volume is 32(exp 3) accretion radii. We examine the influence of numerical procedure on physical behavior. The hydrodynamics is modeled by the 'piecewise parabolic method.' No energy sources (nuclear burning) or sinks (radiation, conduction) are included. The resolution in the vicinity of the accretor is increased by multiply nesting several (5-10) grids around the sphere, each finer grid being a factor of 2 smaller in zone dimension that the next coarser grid. The largest dynamic range (ratio of size of the largest grid to size of the finest zone) is 16,384. This allows us to include a coarse model for the surface of the accretor (vacuum sphere) on the finest grid, while at the same time evolving the gas on the coarser grids. Initially (at time t = 0-10), a shock front is set up, a Mach cone develops, and the accretion column is observable. Eventually the flow becomes unstable, destroying axisymmetry. This happens approximately when the mass accretion rate reaches the values (+/- 10%) predicted by the Bondi-Hoyle accretion formula (factor of 2 included). However, our three-dimensional models do not show the highly dynamic flip-flop flow so prominent in two-dimensional calculations performed by other authors. The flow, and thus the accretion rate of all quantities, shows quasi-periodic (P approximately equals 5) cycles between quiescent and active states. The interpolation formula proposed in an accompanying paper is found to follow the collected numerical data to within approximately 30%. The specific angular momentum accreted is of the same order of magnitude as the values previously found for two-dimensional flows.

Ruffert, Maximilian↗
NASA NTRS1997

On the Dramatic Spin-up/Spin-Down Torque Reversals in Accreting Pulsars

Dramatic torque reversals between spin-up and spin-down have been observed in half of the persistent X-ray pulsars monitored by the Burst and Transient Space Experiment (BATSE) all-sky monitor on the Compton Gamma Ray Observatory. Theoretical models developed to explain early pulsar timing data can explain spin-down torques via a disk-magnetosphere interaction if the star nearly corotates with the inner accretion disk. To produce the observed BATSE torque reversals, however, these equilibrium models require the disk to alternate between two mass accretion rates, with M+/- producing accretion torques of similar magnitude but always of opposite sign. Moreover, in at least one pulsar (GX 1+4) undergoing secular spin-down, the neutron star spins down faster during brief (approximately 20 day) hard X-ray flares-this is opposite the correlation expected from standard theory, assuming that BATSE pulsed flux increases with mass accretion rate. The 10 day to 10 yr intervals between torque reversals in these systems are much longer than any characteristic magnetic or viscous timescale near the inner disk boundary and are more suggestive of a global disk phenomenon. We discuss possible explanations of the observed torque behavior. Despite the preferred sense of rotation defined by the binary orbit, the BATSE observations are surprisingly consistent with an earlier suggestion for GX 1+4: the disks in these systems somehow alternate between episodes of prograde and retrograde rotation. We are unaware of any mechanism that could produce a stable retrograde disk in a binary undergoing Roche lobe overflow, but such flip-flop behavior does occur in numerical simulations of wind-fed systems. One possibility is that the disks in some of these binaries are fed by an X-ray-excited wind.

Nelson, Robert W.↗
NASA NTRS1998

Summary of Proton Test on the Quick Logic QL3025 at Indiana University

This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

Katz, Richard↗
NASA NTRS1998

Summary of Proton Test on the Actel A1280A at Indiana University

A summary of tests performed at the Indiana University Cycl,oltron Facility, on the Actel A1280A circuit device is described. The intent of the study was to investigate the proton response of the hard-wired S-Module flip-flops with a large sample size. This device is sensitive to protons for S-Modules. The device's performance in the test is shown in graphs, and was typical for devices of this class.

Katz, Richard↗
NASA NTRS2003

The Thiamin Pyrophosphate-Motif

Using databases the authors have identified a common thiamin pyrophosphate (TPP)-motif in the family of functionally diverse TPP-dependent enzymes. This common motif consists of multimeric organization of subunits, two catalytic centers, common amino acid sequence, and specific contacts to provide a flip-flop, or alternate site, mechanism of action. Each catalytic center [PP:PYR] is formed at the interface of the PP-domain binding the magnesium ion, pyrophosphate and aminopyrimidine ring of TPP, and the PYR-domain binding the aminopyrimidine ring of that cofactor. A pair of these catalytic centers constitutes the catalytic core [PP:PYR]* within these enzymes. Analysis of the structural elements of this catalytic core reveals novel definition of the common amino acid sequences, which are GX@&(G)@XXGQ, and GDGX25-30 within the PP- domain, and the E&(G)@XXG@ within the PYR-domain, where Q, corresponds to a hydrophobic amino acid. This TPP-motif provides a novel tool for annotation of TPP-dependent enzymes useful in advancing functional proteomics.

Dominiak, Paulina M.↗
NASA NTRS2004

The Conservation of Structure and Mechanism of Catalytic Action in a Family of Thiamin Pyrophosphate (TPP)-dependent Enzymes

Thiamin pyrophosphate (TPP)-dependent enzymes are a divergent family of TPP and metal ion binding proteins that perform a wide range of functions with the common decarboxylation steps of a -(O=)C-C(OH)- fragment of alpha-ketoacids and alpha- hydroxyaldehydes. To determine how structure and catalytic action are conserved in the context of large sequence differences existing within this family of enzymes, we have carried out an analysis of TPP-dependent enzymes of known structures. The common structure of TPP-dependent enzymes is formed at the interface of four alpha/beta domains from at least two subunits, which provide for two metal and TPP-binding sites. Residues around these catalytic sites are conserved for functional purpose, while those further away from TPP are conserved for structural reasons. Together they provide a network of contacts required for flip-flop catalytic action within TPP-dependent enzymes. Thus our analysis defines a TPP-action motif that is proposed for annotating TPP-dependent enzymes for advancing functional proteomics.

Dominiak, P.↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
NASA NTRS2004

Tradeoffs in Flight Design Upset Mitigation in State of the Art FPGAs: Hardened by Design vs. Design Level Hardening

This presentation compares and contrasts the effectiveness and the system/designer impacts of the two main approaches to upset hardening: the Actel approach (RTSX-S and RTAX-S) of low-level (inside each flip-flop) triplication and the Xilinx approach (Virtex and Virtex2) of design-level triplication of both functional blocks and voters. The effectiveness of these approaches is compared using measurements made in conjunction with each of the FPGAs' manufacturer: for Actel, published data [1] and for Xilinx, recent results from the Xilinx SEE Test Consortium (note that the author is an active and founding member). The impacts involve Actel advantages in the areas of transistor-utilization efficiency and minimizing designer involvement in the triplication while the Xilinx advantages relate to the ability to custom tailor upset hardness and the flexibility of re-configurability. Additionally, there are currently clear Xilinx advantages in available features such as the number of I/O's, logic cells, and RAM blocks as well as speed. However, the advantage of the Actel anti-fuses for configuration over the Xilinx SRAM cells is that the latter need additional functionality and external circuitry (PROMs and, at least a watchdog timer) for configuration and configuration scrubbing. Further, although effectively mitigated if done correctly, the proton upset-ability of the Xilinx FPGAs is a concern in severe proton-rich environments. Ultimately, both manufacturers' upset hardening is limited by SEFI (single-event functional interrupt) rates where it appears the Actel results are better although the Xilinx Virtex2-family result of about one SEFI in 65 device-years in solar-min GCR (the more intense part of the galactic cosmic-ray background) should be acceptable to most missions

radiation effects↗
NASA NTRS2006

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Field Programmable Gate Arrays↗
NASA NTRS2013

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

DuMonthier, Jeffrey↗
NASA NTRS2013

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗
DOE OSTI2026

Surrogate Neural Architecture Codesign Package (SNAC-Pack)

Neural architecture search (NAS) is a powerful approach for automating model design, but existing methods often optimize for accuracy alone or rely on proxy metrics such as bit operations (BOPs) that correlate poorly with hardware cost. This gap is particularly large for FPGA deployment, where cost is dominated by a multi-dimensional budget of lookup tables, DSPs, flip-flops, BRAM, and latency. We present the Surrogate Neural Architecture Codesign Package (SNAC-Pack), an open-source AutoML framework for hardware-aware neural architecture codesign and end-to-end FPGA deployment. SNAC-Pack runs a multi-objective global search with Optuna and NSGA-II, loading trials to a shared SQLite store that enables parallel workers across compute nodes. A hardware surrogate model outputs per-trial resource and latency estimates, avoiding the synthesis cost that would otherwise dominate the search loop. A local search stage then applies quantization-aware training (QAT) together with iterative magnitude pruning in a combined compression loop, after which the final model is synthesized to FPGA firmware via the hls4ml Python library. A YAML configuration and an optional agentic frontend let users run the pipeline on new datasets without modifying the framework. We demonstrate SNAC-Pack on jet classification at the Large Hadron Collider and superconducting qubit readout, discovering compact architectures that match or exceed strong baselines on the task metric while reducing FPGA resource utilization and, in the qubit readout case, reducing the design space exploration process from months of manual fine-tuning to hours of automated search.

Weitz, Jason [UC, San Diego]↗