Results for “Digital circuits” — Page 59

NASA NTRS1996

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources

Increased penetration of power electronics interfaced Distributed Energy Resources (DER) like PV, electric vehicle and battery storage in the distribution system (both in numbers and sizes) may cause bi-directional power flows under normal operation. In addition, they contribute low fault current under short circuit conditions. These two changes can impact the proper operation of legacy protection systems. This can add additional challenges during weak grid and islanded operation. In this research, traveling wave (high frequency) signature based protection scheme is proposed for future distribution systems. Simulations are performed under different transient scenarios to provide insight into the high frequency signatures to show the traveling wave behavior. Finally, this paper discusses the importance of sensing and digital processing requirements for traveling-wave protection in distribution system.

41 EE - Solar Energy Technologies Office (EE-4S)↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources: Preprint

Increased penetration of power electronics interfaced Distributed Energy Resources (DER) like PV, electric vehicle and battery storage in the distribution system (both in numbers and sizes) may cause bi-directional power flows under normal operation. In addition, they contribute low fault current under short circuit conditions. These two changes can impact the proper operation of legacy protection systems. This can add additional challenges during weak grid and islanded operation. In this research, traveling wave (high frequency) signature based protection scheme is proposed for future distribution systems. Simulations are performed under different transient scenarios to provide insight into the high frequency signatures to show the traveling wave behavior. Finally, this paper discusses the importance of sensing and digital processing requirements for traveling-wave protection in distribution system.

41 EE - Solar Energy Technologies Office (EE-4S)↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources

Increased penetration of power electronics interfaced Distributed Energy Resources (DER) like PV, electric vehicle and battery storage in the distribution system (both in numbers and sizes) may cause bi-directional power flows under normal operation. In addition, they contribute low fault current under short circuit conditions. These two changes can impact the proper operation of legacy protection systems. This can add additional challenges during weak grid and islanded operation. In this research, traveling wave (high frequency) signature based protection scheme is proposed for future distribution systems. Simulations are performed under different transient scenarios to provide insight into the high frequency signatures to show the traveling wave behavior. Finally, this paper discusses the importance of sensing and digital processing requirements for traveling-wave protection in distribution system.

41 EE - Solar Energy Technologies Office (EE-4S)↗

NASA NTRS2008

Instrumentation System Diagnoses a Thermocouple

An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.

Perotti, Jose↗

NASA NTRS1981

Minus 55 to plus 200 deg C 12 bit analog-to-digital converter

A 12 bit successive approximation analog to digital converter that offers moderately high speed precision data conversion at a reasonable level of cost and complexity is studied. The ADCH10HT extends this capability over a temperature range of -55 to +200 C. No missing-code performance is maintained over the entire temperature range. The converter is completely self-contained with internal clock and +10 volt reference. The CMOS devices offer low power dissipation, so that the internal temperature of the hybrid circuit does not rise as much from self heating. In CMOS circuits, pn junction leakage currents are returned to the supplies so that the logic keeps working at temperatures up to 250 C.

Smith, L. R.↗

NASA NTRS1983

Integrated optical circuits for numerical computation

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

Verber, C. M.↗

NASA NTRS1993

A low-power battery ampere-hour meter

A digital device has been developed to meter the current drain of a battery in ampere hours. The device consists of a voltage controlled oscillator (VCO), a frequency divider, an accumulator, and a liquid crystal display. A voltage proportional to load current is converted into a clock signal whose pulse rate is scaled by the frequency divider to the desired engineering units. Final output pulses are counted and displayed. The use of MOSFET and CMOS integrated circuits allows continuous battery-powered operation over a 3-month time period to an accuracy of +/- 2 percent. The instrument will find application where accurate monitoring of battery charge/discharge status is required over long time intervals.

Tripp, John S.↗

DOE OSTI2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit data streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across application kernels. However, emerging streaming applications at the edge (scientific instruments, sensor networks, network processing) perform much more than digital signal processing and often are data and input dependent. This leads to extremely variable kernel execution times, severely impacting the throughput of the entire pipeline if resources are only statically allocated. Therefore, in this paper, we propose DRIPS — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We present a unified compiler framework to facilitate the mapping of a given streaming application onto the DRIPS CGRA architecture. The experimental results show that DRIPS achieves an average throughput improvement of 1.46$\times$ across a set of representative applications over a statically partitioned solution. The additional area overhead to enable dynamic rebalancing consumes 16.34% of the entire area for a 5x5 CGRA prototype.

Tan, Cheng↗

DOE OSTI2025

Ground state energy and magnetization curve of a frustrated magnetic system from real-time evolution on a digital quantum processor

Models of interacting many-body quantum systems that may realize new exotic phases of matter, notably quantum spin liquids, are challenging to study using even state-of-the-art classical methods such as tensor network simulations. Quantum computing provides a promising route for overcoming these difficulties to find ground states, dynamics, and more. In this paper, we argue that recently developed hybrid quantum-classical algorithms based on real-time evolution are promising methods for solving a particularly important model in the search for spin liquids, the antiferromagnetic Heisenberg model on the two-dimensional kagome lattice. We show how to construct efficient quantum circuits to implement time evolution for the model and to evaluate key observables on the quantum computer, and we argue that the method has favorable scaling with increasing system size. We then restrict to a 12-spin star plaquette from the kagome lattice and a related 8-spin system, and we give an empirical demonstration on these small systems that the hybrid algorithms can efficiently find the ground state energy and the magnetization curve. For these demonstrations, we use four levels of approximation: exact state vectors, exact state vectors with statistical noise from sampling, noisy classical emulators, and (for the 8-spin system only) real quantum hardware, specifically the Quantinuum H1-1 processor; for the noisy simulations and hardware demonstration, we also employ error mitigation strategies based on the symmetries of the Hamiltonian. Our results strongly suggest that these hybrid algorithms present a promising direction for studying quantum spin liquids and more generally for resolving important unsolved problems in condensed matter theory and beyond.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1993

Low-Jitter Digital Rate Multiplier

Jitter in digital rate multiplier reduced by improved method involving use of two slightly different minor clock periods. Original application to divide measured period of spin of spacecraft into large number of equal subintervals, by counting cycles of master oscillator running at high frequency. Method also used to reduce jitter in other situations necessary to generate equal subintervals from synchronizing clock signal of arbitrary period. Particularly valuable in situations where synchronizing signals lost temporarily and where drift in analog circuit unacceptable.

Katz, Richard B.↗

DOE OSTI2020

Driven-dissipative quantum mechanics on a lattice: Simulating a fermionic reservoir on a quantum computer

The driven-dissipative many-body problem remains one of the most challenging unsolved problems in quantum mechanics. The advent of quantum computers may provide a unique platform for efficiently simulating such driven-dissipative systems. But, there are many choices for how one can engineer the reservoir. One can simply employ ancilla qubits to act as a reservoir and then digitally simulate them via algorithmic cooling. A more attractive approach, which allows one to simulate an infinite reservoir, is to integrate out the bath degrees of freedom and describe the driven-dissipative system via a master equation, that can also be simulated on a quantum computer. In this work, we consider the particular case of noninteracting electrons on a lattice driven by an electric field and coupled to a fermionic thermostat. Then, we provide two different quantum circuits: the first one reconstructs the full dynamics of the system using Trotter steps, while the second one dissipatively prepares the final nonequilibrium steady state in a single step. We run both circuits on the IBM quantum experience. For circuit (i), we achieved up to five Trotter steps. When partial resets become available on quantum computers, we expect that the maximum simulation time can be significantly increased. Lastly, the methods developed here suggest generalizations that can be applied to simulating interacting driven-dissipative systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

NASA NTRS1974

Computer program CORDET

A FORTRAN 4 computer program provides convenient simulation of an all-digital phase-lock loop (DPLL). The DPLL forms the heart of the Omega navigation receiver prototype. Through the DPLL, the phase of the 10.2 KHz Omega signal is estimated when the true signal phase is contaminated with noise. This investigation has provided a convenient means of evaluating loop performance in a variety of noise environments, and has proved to be a useful tool for evaluating design changes. The goals of the simulation are to: (1) analyze the circuit on a bit-by-bit level in order to evaluate the overall design; (2) see easily the effects of proposed design changes prior to actual breadboarding; and (3) determine the optimum integration time for the DPLL in an environment typical of general aviation conditions.

Palkovic, R. A.↗

NASA NTRS2013

Submillimeter Planetary Atmospheric Chemistry Exploration Sounder

Planetary Atmospheric Chemistry Exploration Sounder (SPACES), a high-sensitivity laboratory breadboard for a spectrometer targeted at orbital planetary atmospheric analysis. The frequency range is 520 to 590 GHz, with a target noise temperature sensitivity of 2,500 K for detecting water, sulfur compounds, carbon compounds, and other atmospheric constituents. SPACES is a prototype for a powerful tool for the exploration of the chemistry and dynamics of any planetary atmosphere. It is fundamentally a single-pixel receiver for spectral signals emitted by the relevant constituents, intended to be fed by a fixed or movable telescope/antenna. Its front-end sensor translates the received signal down to the 100-MHz range where it can be digitized and the data transferred to a spectrum analyzer for processing, spectrum generation, and accumulation. The individual microwave and submillimeter wave components (mixers, LO high-powered amplifiers, and multipliers) of SPACES were developed in cooperation with other programs, although with this type of instrument in mind. Compared to previous planetary and Earth science instruments, its broad bandwidth (approx. =.13%) and rapid tunability (approx. =.10 ms) are new developments only made possible recently by the advancement in submillimeter circuit design and processing at JPL.

Schlecht, Erich T.↗

DOE OSTI2022

Medium Voltage Energy Hub Based on Multilevel Cascaded H Bridge-Dual Active Bridge Back-to-Back Converter for Power Distribution Feeders Interconnection and Multiple Simultaneous Grid Services

This paper presents a medium voltage energy hub based on a modular design of a multilevel cascaded H bridge (CHB)-dual active bridge (DAB) converter. The energy hub composed of the two CHB-DAB modules with a back-to-back topology can be utilized as a grid interconnection component between distribution feeders. The energy hub can provide multiple simultaneous grid services such as voltage regulation, power factor correction, as well as active power flow control between the connected feeders, contributing to grid flexibility, efficiency, reliability, and resilience. Circuit structure and control schemes for the energy hub including both local controllers for each converter and outer loop controllers are proposed to enable simultaneous grid services with coordination to prevent the overloading of the hub. To validate the performance of the hub, the hub system is interconnected between two IEEE 4-bus feeders and provides voltage regulation for both feeders, while controlling active power flow between them. The system and the feeders are implemented in Real-Time Digital Simulator (RTDS) for real-time simulation verification.

Choi, Jongchan↗

DOE OSTI2025

Unification of finite symmetries in the simulation of many-body systems on quantum computers

Symmetry is fundamental in the description and simulation of quantum systems. Leveraging symmetries in classical simulations of many-body quantum systems can result in significant overhead due to the exponentially growing size of some symmetry groups as the number of particles increases. Quantum computers hold the promise of achieving exponential speedup in simulating quantum many-body systems; however, a general method for utilizing symmetries in quantum simulations has not yet been established. In this work, we present a unified framework for incorporating symmetry group transforms on quantum computers to simulate many-body systems. The core of our approach lies in the development of efficient quantum circuits for symmetry-adapted projection onto irreducible representations of a group or pairs of commuting groups. We provide resource estimations for common groups, including the cyclic and permutation groups. Our algorithms demonstrate the capability to prepare coherent superpositions of symmetry-adapted states and to perform quantum evolution across a wide range of models in condensed-matter physics and ab initio electronic structure in quantum chemistry. Specifically, we execute a symmetry-adapted quantum subroutine for small molecules in first-quantization on noisy hardware and demonstrate the emulation of symmetry-adapted quantum phase estimation for preparing coherent superpositions of quantum states in various irreducible representations of a symmetry group. In addition, we present a discussion of open problems regarding treating symmetries in digital quantum simulations of many-body systems, paving the way for future systematic investigations into leveraging symmetries quantumly for practical quantum advantage. The broad applicability and rigorous resource estimation for symmetry transformations make our framework appealing for achieving provable quantum advantage on fault-tolerant quantum computers, especially for symmetry-related properties.

quantum algorithms↗