Low-Jitter Digital Rate Multiplier

Abstract

Jitter in digital rate multiplier reduced by improved method involving use of two slightly different minor clock periods. Original application to divide measured period of spin of spacecraft into large number of equal subintervals, by counting cycles of master oscillator running at high frequency. Method also used to reduce jitter in other situations necessary to generate equal subintervals from synchronizing clock signal of arbitrary period. Particularly valuable in situations where synchronizing signals lost temporarily and where drift in analog circuit unacceptable.