The Mars Pathfinder Commercial Hardware and Microgyro (CHuG) Experiment: Lessons Already
The Commercial Hardware and Microgyro (CHmG) experiment was designed to demonstrate the.
Mars Pathfinder↗
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Results for “HARDWARE”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A Multichip Module Based RISC Processor with Programmable Hardware
A Multichip Module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's new 'cheaper, faster, better' missions.
RISC Processor↗
Microbial Characterization of Internal Active Thermal Control System (IATCS) Hardware Surfaces after Five Years of Operation in the International Space Station
A flex hose assembly containing aqueous coolant from the International Space Station (ISS) Internal Active Thermal Control System (IATCS) consisting of a 2 foot section of Teflon hose and quick disconnects (QDs) and a Special Performance Checkout Unit (SPCU) heat exchanger containing separate channels of IATCS coolant and iodinated water used to cool spacesuits and Extravehicular Mobility Units (EMUS) were returned for destructive analyses on Shuttle return to flight mission STS-114. The original aqueous IATCS coolant used in Node 1, the Laboratory Module, and the Airlock consisted of water, borate (pH buffer), phosphate (corrosion control), and silver sulfate (microbiological control) at a pH of 9.5 +/- 0.5. Chemical changes occurred after on-orbit implementation including a decrease to pH 8.4 due to the diffusion of carbon dioxide through the Teflon hoses, an increase in nickel ions due to general corrosion of heat exchanger braze coatings, a decrease in phosphate concentration due to precipitation of nickel phosphate, and the rapid disappearance of silver ions due to deposition on hardware surfaces. Also associated with the coolant chemistry changes was an increase in planktonic microorganisms from less than 100 colony forming units (CFU) per 100 ml to approximately 1 million CFU per 100 ml. Attachment and growth of microorganisms to the system surfaces (biofilm) was suspected due to the levels of planktonic microorganisms in the coolant. Biofilms can reduce coolant flow, reduce heat transfer, amplify degradation of system materials initiated by chemical corrosion, and enhance mineral scale formation.
Roman, Monsi C.↗
A Hardware-in-the-Loop Simulator for Software Development for a Mars Airplane
Draper Laboratory recently developed a Hardware-In-The-Loop Simulator (HILSIM) to provide a simulation of the Aerial Regional-scale Environmental Survey (ARES) airplane executing a mission in the Martian environment. The HILSIM was used to support risk mitigation activities under the Planetary Airplane Risk Reduction (PARR) program. PARR supported NASA Langley Research Center's (LaRC) ARES proposal efforts for the Mars Scout 2011 opportunity. The HILSIM software was a successful integration of two simulation frameworks, Draper's CSIM and NASA LaRC's Langley Standard Real-Time Simulation in C++ (LaSRS++).
Slagowski, Stefan E.↗
A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response
We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.
gyroscope controls↗
Automated Eddy Current Inspection on Space Shuttle Hardware
Over the life time of the Space Shuttle program, metal parts used for the Reusable Solid Rocket Motors (RSRMs) have been nondestructively inspected for cracks and surface breaking discontinuities using magnetic particle (steel) and penetrant methods. Although these inspections adequately screened for critical sized cracks in most regions of the hardware, it became apparent after detection of several sub-critical flaws that the processes were very dependent on operator attentiveness and training. Throughout the 1990's, eddy current inspections were added to areas that had either limited visual access or were more fracture critical. In the late 1990's. a project was initiated to upgrade NDE inspections with the overall objective of improving inspection reliability and control. An automated eddy current inspection system was installed in 2001. A figure shows one of the inspection bays with the robotic axis of the system highlighted. The system was programmed to inspect the various case, nozzle, and igniter metal components that make up an RSRM. both steel and aluminum. For the past few years, the automated inspection system has been a part of the baseline inspection process for steel components. Although the majority of the RSRM metal part inventory ts free of detectable surface flaws, a few small, sub-critical manufacturing defects have been detected with the automated system. This paper will summarize the benefits that have been realized with the current automated eddy current system, as well as the flaws that have been detected.
Hartmann, John↗
Performance of the Extravehicular Mobility Unit (EMU): Airlock Coolant Loop Recovery (A/L CLR) Hardware - Phase II
An EMU water processing kit (Airlock Coolant Loop Recovery A/L CLR) was developed as a corrective action to Extravehicular Mobility Unit (EMU) coolant flow disruptions experienced on the International Space Station (ISS) in May of 2004 and thereafter. Conservative schedules for A/L CLR use and component life were initially developed and implemented based on prior analysis results and analytical modeling. The examination of postflight samples and EMU hardware in November of 2006 indicated that the A/L CLR kits were functioning well and had excess capacity that would allow a relaxation of the initially conservative schedules of use and component life. A relaxed use schedule and list of component lives was implemented thereafter. Since the adoption of the relaxed A/L CLR schedules of use and component lives, several A/L CLR kit components, transport loop water samples and sensitive EMU transport loop components have been examined to gage the impact of the relaxed requirements. The intent of this paper is to summarize the findings of that evaluation, and to outline updated schedules for A/L CLR use and component life.
Steele, John↗
Hardware Implementation of Serially Concatenated PPM Decoder
A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in operation of the decoder. This is accomplished in the receiver by transmitting only a subset consisting of the likelihoods that correspond to time slots containing the largest numbers of observed photons during each PPM symbol period. The assumed number of observed photons in the remaining time slots is set to the mean of a noise slot. In low background noise, the selection of a small subset in this manner results in only negligible loss. Other features of the decoder design to reduce complexity and increase speed include (1) quantization of metrics in an efficient procedure chosen to incur no more than a small performance loss and (2) the use of the max-star function that allows sum of exponentials to be computed by simple operations that involve only an addition, a subtraction, and a table lookup. Another prominent feature of the design is a provision for access to interleaver and de-interleaver memory in a single clock cycle, eliminating the multiple clock-cycle latency characteristic of prior interleaver and de-interleaver designs.
Moision, Bruce↗
Big Science, Small-Budget Space Experiment Package Aka MISSE-5: A Hardware And Software Perspective
Conducting space experiments with small budgets is a fact of life for many design groups with low-visibility science programs. One major consequence is that specialized space grade electronic components are often too costly to incorporate into the design. Radiation mitigation now becomes more complex as a result of being restricted to the use of commercial off-the-shelf (COTS) parts. Unique hardware and software design techniques are required to succeed in producing a viable instrument suited for use in space. This paper highlights some of the design challenges and associated solutions encountered in the production of a highly capable, low cost space experiment package.
Krasowski, Michael↗
J-2X Upper Stage Engine: Hardware and Testing 2009
Mission: Common upper stage engine for Ares I and Ares V. Challenge: Use proven technology from Saturn X-33, RS-68 to develop the highest Isp GG cycle engine in history for 2 missions in record time . Key Features: LOX/LH2 GG cycle, series turbines (2), HIP-bonded MCC, pneumatic ball-sector valves, on-board engine controller, tube-wall regen nozzle/large passively-cooled nozzle extension, TEG boost/cooling . Development Philosophy: proven hardware, aggressive schedule, early risk reduction, requirements-driven.
Buzzell, James C.↗
Hardware Implementation of a Bilateral Subtraction Filter
A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for its position in the window as well as the pixel value for the central pixel of the window. The absolute difference between these two pixel values is calculated and used as an address in a lookup table. Each processing element has a lookup table, unique for its position in the window, containing the weight coefficients for the Gaussian function for that position. The pixel value is multiplied by the weight, and the outputs of the processing element are the weight and pixel-value weight product. The products and weights are fed to the adder tree. The sum of the products and the sum of the weights are fed to the divider, which computes the sum of products the sum of weights. The output of the divider is denoted the bilateral smoothed image. The smoothing function is a simple weighted average computed over a 3 3 subwindow centered in the 9 9 window. After smoothing, the image is delayed by an additional amount of time needed to match the processing time for computing the bilateral smoothed image. The bilateral smoothed image is then subtracted from the 3 3 smoothed image to produce the final output. The prototype filter as implemented in a commercially available FPGA processes one pixel per clock cycle. Operation at a clock speed of 66 MHz has been demonstrated, and results of a static timing analysis have been interpreted as suggesting that the clock speed could be increased to as much as 100 MHz.
Huertas, Andres↗
Utilization of ISS to Develop and Test Operational Concepts and Hardware for Low-Gravity Terrestrial EVA
NASA has considerable experience in two areas of Extravehicular Activities (EVA). The first can be defined as microgravity, orbital EVAs. This consists of everything done in low Earth orbit (LEO), from the early, proof of concept EVAs conducted during the Gemini program of the 1960s, to the complex International Space Station (ISS) assembly tasks of the first decade of the 21st century. The second area of expertise is comprised of those EVAs conducted on the lunar surface, under a gravitational force one-sixth that of Earth. This EVA expertise encapsulates two extremes - microgravity and Earthlike gravitation - but is insufficient as humans expand their exploration purview, most notably with respect to spacewalks conducted on very low-gravity bodies, such as near- Earth objects (NEO) and the moons of Mars. The operational and technical challenges of this category of EVA have yet to be significantly examined, and as such, only a small number of operational concepts have been proposed thus far. To ensure mission success, however, EVA techniques must be developed and vetted to allow the selection of operational concepts that can be utilized across an assortment of destinations whose physical characteristics vary. This paper examines the utilization of ISS-based EVAs to test operational concepts and hardware in preparation for a low-gravity terrestrial EVA. While the ISS cannot mimic some of the fundamental challenges of a low-gravity terrestrial EVA - such as rotation rate and surface composition - it may be the most effective test bed available.
Gast, Matthew A.↗
Hardware-Independent Proofs of Numerical Programs
On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved
Boldo, Sylvie↗
Theorem Proving in Intel Hardware Design
For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.
O'Leary, John↗
Demonstration of an Aerocapture GN and C System Through Hardware-in-the-Loop Simulations
Aerocapture is an orbit insertion maneuver in which a spacecraft flies through a planetary atmosphere one time using drag force to decelerate and effect a hyperbolic to elliptical orbit change. Aerocapture employs a feedback Guidance, Navigation, and Control (GN&C) system to deliver the spacecraft into a precise postatmospheric orbit despite the uncertainties inherent in planetary atmosphere knowledge, entry targeting and aerodynamic predictions. Only small amounts of propellant are required for attitude control and orbit adjustments, thereby providing mass savings of hundreds to thousands of kilograms over conventional all-propulsive techniques. The Analytic Predictor Corrector (APC) guidance algorithm has been developed to steer the vehicle through the aerocapture maneuver using bank angle control. Through funding provided by NASA's In-Space Propulsion Technology Program, the operation of an aerocapture GN&C system has been demonstrated in high-fidelity simulations that include real-time hardware in the loop, thus increasing the Technology Readiness Level (TRL) of aerocapture GN&C. First, a non-real-time (NRT), 6-DOF trajectory simulation was developed for the aerocapture trajectory. The simulation included vehicle dynamics, gravity model, atmosphere model, aerodynamics model, inertial measurement unit (IMU) model, attitude control thruster torque models, and GN&C algorithms (including the APC aerocapture guidance). The simulation used the vehicle and mission parameters from the ST-9 mission. A 2000 case Monte Carlo simulation was performed and results show an aerocapture success rate of greater than 99.7%, greater than 95% of total delta-V required for orbit insertion is provided by aerodynamic drag, and post-aerocapture orbit plane wedge angle error is less than 0.5 deg (3-sigma). Then a real-time (RT), 6-DOF simulation for the aerocapture trajectory was developed which demonstrated the guidance software executing on a flight-like computer, interfacing with a simulated IMU and simulated thrusters, with vehicle dynamics provided by an external simulator. Five cases from the NRT simulations were run in the RT simulation environment. The results compare well to those of the NRT simulation thus verifying the RT simulation configuration. The results of the above described simulations show the aerocapture maneuver using the APC algorithm can be accomplished reliably and the algorithm is now at TRL-6. Flight validation is the next step for aerocapture technology development.
Masciarelli, James↗
Hardware Implementation of COTS Avionics System on Unmanned Aerial Vehicle Platforms
Unmanned Aerial Vehicles (UAVs) can serve as low cost and low risk platforms for flight testing in Aeronautics research. The NASA Exploration Aerial Vehicle (EAV) and Experimental Sensor-Controlled Aerial Vehicle (X-SCAV) UAVs were developed in support of control systems research at NASA Ames Research Center. The avionics hardware for both systems has been redesigned and updated, and the structure of the EAV has been further strengthened. Preliminary tests show the avionics operate properly in the new configuration. A linear model for the EAV also was estimated from flight data, and was verified in simulation. These modifications and results prepare the EAV and X-SCAV to be used in a wide variety of flight research projects.
Yeh, Yoo-Hsiu↗
Workmanship Challenges for NASA Mission Hardware
This slide presentation reviews several challenges in workmanship for NASA mission hardware development. Several standards for NASA workmanship exist, that are required for all programs, projects, contracts and subcontracts. These Standards contain our best known methods for avoiding past assembly problems and defects. These best practices may not be available if suppliers are used who are not compliant with them. Compliance includes having certified operators and inspectors. Some examples of problems that have occured from the lack of requirements flow-down to contractors are reviewed. The presentation contains a detailed example of the challenge in regards to The Packaging "Design" Dilemma.
Plante, Jeannette↗
TRL Assessment of Solar Sail Technology Development Following the 20-Meter System Ground Demonstrator Hardware Testing
The NASA In-Space Propulsion Technology (ISPT) Projects Office sponsored two separate, independent solar sail system design and development demonstration activities during 2002-2005. ATK Space Systems of Goleta, CA was the prime contractor for one development team and L' Garde, Inc. of Tustin, CA was the prime contractor for the other development team. The goal of these activities was to advance the technology readiness level (TRL) of solar sail propulsion from 3 towards 6 by the year 2006. Component and subsystem fabrication and testing were completed successfully, including the ground deployment of 10-meter and 20-meter demonstration hardware systems under vacuum conditions. The deployment and structural testing of the 20-meter solar sail systems was conducted in the 30 meter diameter Space Power Facility thermal-vacuum chamber at NASA Glenn Plum Brook in April though August, 2005. This paper will present the results of the TRL assessment following the solar sail technology development activities associated with the design, development, analysis and testing of the 20-meter system ground demonstrators.
Young, Roy M.↗