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At least 1,009 records · Page 56

High-Density, High-Bandwidth, Multilevel Holographic Memory

A proposed holographic memory system would be capable of storing data at unprecedentedly high density, and its data transfer performance in both reading and writing would be characterized by exceptionally high bandwidth. The capabilities of the proposed system would greatly exceed even those of a state-of-the art memory system, based on binary holograms (in which each pixel value represents 0 or 1), that can hold .1 terabyte of data and can support a reading or writing rate as high as 1 Gb/s. The storage capacity of the state-of-theart system cannot be increased without also increasing the volume and mass of the system. However, in principle, the storage capacity could be increased greatly, without significantly increasing the volume and mass, if multilevel holograms were used instead of binary holograms. For example, a 3-bit (8-level) hologram could store 8 terabytes, or an 8-bit (256-level) hologram could store 256 terabytes, in a system having little or no more size and mass than does the state-of-the-art 1-terabyte binary holographic memory. The proposed system would utilize multilevel holograms. The system would include lasers, imaging lenses and other beam-forming optics, a block photorefractive crystal wherein the holograms would be formed, and two multilevel spatial light modulators in the form of commercially available deformable-mirror-device spatial light modulators (DMDSLMs) made for use in high speed input conversion of data up to 12 bits. For readout, the system would also include two arrays of complementary metal oxide/semiconductor (CMOS) photodetectors matching the spatial light modulators. The system would further include a reference-beam sterring device (equivalent of a scanning mirror), containing no sliding parts, that could be either a liquid-crystal phased-array device or a microscopic mirror actuated by a high-speed microelectromechanical system. Time-multiplexing and the multilevel nature of the DMDSLM would be exploited to enable writing and reading of multilevel holograms. The DMDSLM would also enable transfer of data at a rate of 7.6 Gb/s or perhaps somewhat higher.

Chao, Tien-Hsin↗

NASA Tech Briefs, April 2012

Topics include: Computational Ghost Imaging for Remote Sensing; Digital Architecture for a Trace Gas Sensor Platform; Dispersed Fringe Sensing Analysis - DFSA; Indium Tin Oxide Resistor-Based Nitric Oxide Microsensors; Gas Composition Sensing Using Carbon Nanotube Arrays; Sensor for Boundary Shear Stress in Fluid Flow; Model-Based Method for Sensor Validation; Qualification of Engineering Camera for Long-Duration Deep Space Missions; Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms; Bump Bonding Using Metal-Coated Carbon Nanotubes; In Situ Mosaic Brightness Correction; Simplex GPS and InSAR Inversion Software; Virtual Machine Language 2.1; Multi-Scale Three-Dimensional Variational Data Assimilation System for Coastal Ocean Prediction; Pandora Operation and Analysis Software; Fabrication of a Cryogenic Bias Filter for Ultrasensitive Focal Plane; Processing of Nanosensors Using a Sacrificial Template Approach; High-Temperature Shape Memory Polymers; Modular Flooring System; Non-Toxic, Low-Freezing, Drop-In Replacement Heat Transfer Fluids; Materials That Enhance Efficiency and Radiation Resistance of Solar Cells; Low-Cost, Rugged High-Vacuum System; Static Gas-Charging Plug; Floating Oil-Spill Containment Device; Stemless Ball Valve; Improving Balance Function Using Low Levels of Electrical Stimulation of the Balance Organs; Oxygen-Methane Thruster; Lunar Navigation Determination System - LaNDS; Launch Method for Kites in Low-Wind or No-Wind Conditions; Supercritical CO2 Cleaning System for Planetary Protection and Contamination Control Applications; Design and Performance of a Wideband Radio Telescope; Finite Element Models for Electron Beam Freeform Fabrication Process Autonomous Information Unit for Fine-Grain Data Access Control and Information Protection in a Net-Centric System; Vehicle Detection for RCTA/ANS (Autonomous Navigation System); Image Mapping and Visual Attention on the Sensory Ego-Sphere; HyDE Framework for Stochastic and Hybrid Model-Based Diagnosis; and IMAGESEER - IMAGEs for Education and Research.

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In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory

In-memory computing based on non-volatile resistive memory can significantly improve the energy efficiency of artificial neural networks. However, accurate in situ training has been challenging due to the nonlinear and stochastic switching of the resistive memory elements. One promising analog memory is the electrochemical random-access memory (ECRAM), also known as the redox transistor. Its low write currents and linear switching properties across hundreds of analog states enable accurate and massively parallel updates of a full crossbar array, which yield rapid and energy-efficient training. While simulations predict that ECRAM based neural networks achieve high training accuracy at significantly higher energy efficiency than digital implementations, these predictions have not been experimentally achieved. In this work, we train a 3 × 3 array of ECRAM devices that learns to discriminate several elementary logic gates (AND, OR, NAND). We record the evolution of the network’s synaptic weights during parallel in situ (on-line) training, with outer product updates. Due to linear and reproducible device switching characteristics, our crossbar simulations not only accurately simulate the epochs to convergence, but also quantitatively capture the evolution of weights in individual devices. The implementation of the first in situ parallel training together with strong agreement with simulation results provides a significant advance toward developing ECRAM into larger crossbar arrays for artificial neural network accelerators, which could enable orders of magnitude improvements in energy efficiency of deep neural networks.

97 MATHEMATICS AND COMPUTING↗

The light-sensitive MNOS memory transistor.

The behavior theory of the light-sensitive MNOS memory transistor is developed and supported by presented experimental evidence. It is shown that the nitride, oxide, and silicon space-charge current-field relationships necessary for comparison of theory and experiment can be obtained from steady-state current-voltage measurements on the MNOS device.

Sewell, F. A., Jr.↗

FFT Computation with Systolic Arrays, A New Architecture

The use of the Cooley-Tukey algorithm for computing the l-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started.

Boriakoff, Valentin↗

A Computationally-Efficient, Multi-Mechanism Based Framework for the Comprehensive Modeling of the Evolutionary Behavior of Shape Memory Alloys

The report summarizes the accomplishments made during the 4-year duration of the project. Here, the major emphasis is placed on the different tasks performed by the two research teams; i.e., the modeling activities by the University of Akron (UA) team and the experimental and neutron diffraction studies conducted by the University of Central Florida (UCF) team, during this 4-year period. Further technical details are given in the upcoming sections by UA and UCF for each of the milestones/years (together with the corresponding figures and captions).The project majorly involved the development, validation, and application of a general theoretical model that is capable of capturing the nonlinear hysteretic responses, including pseudoelasticity, shape memory effect, rate-dependency, multi-axiality, asymmetry in tension versus compression response of shape memory alloys. Among the targeted goals for the SMA model was its ability to account for the evolutionary character response (including transient and long term behavior under sustained cycles) for both conventional and high temperature (HT) SMAs, as well as being able to simulate some of the devices which exploit these unique material systems. This required extensive (uniaxial and multi-axial) experiments needed to guide us in calibrating and characterizing the model. Moreover, since the model is formulated on the theoretical notion of internal state variables (ISVs), neutron diffraction experiments were needed to establish the linkage between the micromechanical changes and these ISVs. In addition, the design of the model should allow easy implementation in large scale finite element application to study the behavior of devices making use of these SMA materials under different loading controls. Summary of the activities, progress/achievements made during this period is given below in details for the University of Akron and the University (Section 2.0) of Central Florida (Section 3.0).

Alloys↗

Neuromorphic spintronics

Neuromorphic computing uses brain-inspired principles to design circuits that can perform computational tasks with superior power efficiency to conventional computers. Approaches that use traditional electronic devices to create artificial neurons and synapses are, however, currently limited by the energy and area requirements of these components. Spintronic nanodevices, which exploit both the magnetic and electrical properties of electrons, can increase the energy efficiency and decrease the area of these circuits, and magnetic tunnel junctions are of particular interest as neuromorphic computing elements because they are compatible with standard integrated circuits and can support multiple functionalities. Here, we review the development of spintronic devices for neuromorphic computing. We examine how magnetic tunnel junctions can serve as synapses and neurons, and how magnetic textures, such as domain walls and skyrmions, can function as neurons. We also explore spintronics-based implementations of neuromorphic computing tasks, such as pattern recognition in an associative memory, and discuss the challenges that exist in scaling up these systems.

42 ENGINEERING↗

Trends in reliability modeling technology for fault tolerant systems

Developments in reliability modeling for large fault tolerant avionic computing systems are presented. Issues of state size and complexity, fault coverage, and practical computation are addressed. A two-fold developmental effort is described based on the structural and fault coverage modeling approaches. A technique which was successfully applied to an 865 state pure death stationary Markov model is presented. Of particular interest is a short computer program which executes very quickly to produce reliability results of a large state space model. This model also incorporates fault coverage states for processor, memory, and bus line replaceable units. A second structural reliability modeling scheme is aimed at solving nonstationary Markov models. This technique provides the tool required for studying the reliability of systems with nonconstant failure rates and includes intermittent/transient faults, electronic hardware which exhibits decreasing failure rates, and hydromechanical devices which typically have wearout failure mechanisms. Several aspects of fault coverage, including modeling and data measurement of intermittent/transient faults and latent faults, are elucidated and illustrated. The CARE II (computer-aided reliability estimation) coverage is presented and shortcomings to be eliminated are discussed.

Bavuso, S. J.↗

Surface heat-transfer coefficients of finned cylinders

An investigation to determine and correlate the experimental surface heat-transfer coefficients of finned cylinders with different air-stream cooling arrangements was conducted at the Langley Memorial Aeronautical Laboratory from 1932 to 1938. The investigation covered the determination of the effect of fin width, fin space, fin thickness, and cylinder diameter on the heat transfer. Wind-tunnel tests were made in the free air stream with and without baffles and also with various devices for creating a turbulent air stream. Tests were also made with blower.

Ellerbrock, Herman H , Jr↗

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Attia, John Okyere↗

Complex Oxides for Brain–Inspired Computing: A Review

The fields of brain-inspired computing, robotics, and, more broadly, artificial intelligence (AI) seek to implement knowledge gleaned from the natural world into human-designed electronics and machines. In this review, the opportunities presented by complex oxides, a class of electronic ceramic materials whose properties can be elegantly tuned by doping, electron interactions, and a variety of external stimuli near room temperature, are discussed. The review begins with a discussion of natural intelligence at the elementary level in the nervous system, followed by collective intelligence and learning at the animal colony level mediated by social interactions. An important aspect highlighted is the vast spatial and temporal scales involved in learning and memory. The focus then turns to collective phenomena, such as metal-to-insulator transitions (MITs), ferroelectricity, and related examples, to highlight recent demonstrations of artificial neurons, synapses, and circuits and their learning. First-principles theoretical treatments of the electronic structure, and in situ synchrotron spectroscopy of operating devices are then discussed. The implementation of the experimental characteristics into neural networks and algorithm design is then revewed. Finally, outstanding materials challenges that require a microscopic understanding of the physical mechanisms, which will be essential for advancing the frontiers of neuromorphic computing, are highlighted.

36 MATERIALS SCIENCE↗

Knowledge Distillation for Anomaly Detection

Unsupervised deep learning techniques are widely used to identify anomalous behaviour. The performance of such methods is a product of the amount of training data and the model size. However, the size is often a limiting factor for the deployment on resource-constrained devices. Here, we present a novel procedure based on knowledge distillation for compressing an unsupervised anomaly detection model into a supervised deployable one and we suggest a set of techniques to improve the detection sensitivity. Compressed models perform comparably to their larger counterparts while significantly reducing the size and memory footprint.

Pol, Adrian Alan↗

Nanoscale Deformable Optics

Several missions and instruments in the conceptual design phase rely on the technique of interferometry to create detectable fringe patterns. The intimate emplacement of reflective material upon electron device cells based upon chalcogenide material technology permits high-speed, predictable deformation of the reflective surface to a subnanometer or finer resolution with a very high degree of accuracy. In this innovation, a layer of reflective material is deposited upon a wafer containing (perhaps in the millions) chalcogenic memory cells with the reflective material becoming the front surface of a mirror and the chalcogenic material becoming a means of selectively deforming the mirror by the application of heat to the chalcogenic material. By doing so, the mirror surface can deform anywhere from nil to nanometers in spots the size of a modern day memory cell, thereby permitting realtime tuning of mirror focus and reflectivity to mitigate aberrations caused elsewhere in the optical system. Modern foundry methods permit the design and manufacture of individual memory cells having an area of or equal to the Feature (F) size of the design (assume 65 nm). Fabrication rules and restraints generally require the instantiation of one memory cell to another no closer than 1.5 F, or, for this innovation, 90 nm from its neighbor in any direction. Chalcogenide is a semiconducting glass compound consisting of a combination of chalcogen ions, the ratios of which vary according to properties desired. It has been shown that the application of heat to cells of chalcogenic material cause a large alteration in resistance to the range of 4 orders of magnitude. It is this effect upon which chalcogenidebased commercial memories rely. Upon removal of the heat source, the chalcogenide rapidly cools and remains frozen in the excited state. It has also been shown that the chalcogenide expands in volume because of the applied heat, meaning that the coefficient of expansion of chalcogenic materials is larger than 1. In this innovation, chalcogenidebased cells are addressed (as though they are a memory), and heated and cooled according to well-established criteria. In doing so, the exact size of chalcogenide cell deformation is known and predictable; therefore, the deformation of the reflective surface is, likewise, known and predictable. Control electronics can also be implemented so that a closed-loop feedback can be maintained. Changing the contents of the chalcogenide memory cells can compensate for any change in environmental effects that might cause a change in optical path. This real-time control provides significant control and stability in use conditions.

Strauss, Karl F.↗

Resistance drift in Ge 2 Sb 2 Te 5 phase change memory line cells at low temperatures and its response to photoexcitation

Resistance drift in amorphous Ge 2 Sb 2 Te 5 is experimentally characterized in melt-quenched line cells in the range of 300 K to 125 K and is observed to follow the previously reported power-law behavior with drift coefficients in the range of 0.07 to 0.11 in the dark, linearly decreasing with 1/kT. While these drift coefficients measured in the dark are similar to commonly observed drift coefficients (~0.1) at and above room temperature, measurements under light show a significantly lower drift coefficient (0.05 under illumination vs 0.09 in the dark at 150 K). Periodic on/off switching of light shows a sudden decrease/increase in resistance, attributed to photo-excited carriers, followed by a very slow response (~30 min at 150 K) attributed to contribution of electron traps and slow trap-to-trap charge exchanges. A device-level electronic model is used to relate these experimental findings to gradual charging of electron traps in amorphous Ge 2 Sb 2 Te 5 , which gives rise to growth of a potential barrier for holes in time and, hence, resistance drift.

42 ENGINEERING↗

The Impact on Space Radiation Requirements and Effects on ASIMS

The evolution of highly miniaturized electronic and mechanical systems will be accompanied by new problems and issues regarding the radiation response of these systems in the space environment. In this paper we discuss some of the more prominent radiation problems brought about by miniaturization. For example, autonomous micro-spacecraft will require large amounts of high density memory, most likely in the form of stacked, multichip modules of DRAM's, that must tolerate the radiation environment. However, advanced DRAM's (16 to 256 Mbit) are quite susceptible to radiation, particularly single event effects, and even exhibit new radiation phenomena that were not a problem for older, less dense memory chips. Another important trend in micro-spacecraft electronics is toward the use of low-voltage microelectronic systems that consume less power. However, the reduction in operating voltage also caries with it an increased susceptibility to radiation. In the case of application specific integrated microcircuits (ASIM's), advanced devices of this type, such as high density field programmable gate arrays (FPGA's) exhibit new single event effects (SEE), such as single particle reprogramming of anti-fuse links. New advanced bipolar circuits have been shown recently to degrade more rapidly in the low dose rate space environment than in the typical laboratory total dose radiation test used to qualify such devices. Thus total dose testing of these parts is no longer an appropriately conservative measure to be used for hardness assurance. We also note that the functionality of micromechanical Si-based devices may be altered due to the radiation-induced deposition of charge in the oxide passivation layers.

Barnes, C.↗

Electrically Variable or Programmable Nonvolatile Capacitors

Electrically variable or programmable capacitors based on the unique properties of thin perovskite films are undergoing development. These capacitors show promise of overcoming two important deficiencies of prior electrically programmable capacitors: Unlike in the case of varactors, it is not necessary to supply power continuously to make these capacitors retain their capacitance values. Hence, these capacitors may prove useful as components of nonvolatile analog and digital electronic memories. Unlike in the case of ferroelectric capacitors, it is possible to measure the capacitance values of these capacitors without changing the values. In other words, whereas readout of ferroelectric capacitors is destructive, readout of these capacitors can be nondestructive. A capacitor of this type is a simple two terminal device. It includes a thin film of a suitable perovskite as the dielectric layer, sandwiched between two metal or metal oxide electrodes (for example, see Figure 1). The utility of this device as a variable capacitor is based on a phenomenon, known as electrical-pulse-induced capacitance (EPIC), that is observed in thin perovskite films and especially in those thin perovskite films that exhibit the colossal magnetoresistive (CMR) effect. In EPIC, the application of one or more electrical pulses that exceed a threshold magnitude (typically somewhat less than 1 V) gives rise to a nonvolatile change in capacitance. The change in capacitance depends on the magnitude duration, polarity, and number of pulses. It is not necessary to apply a magnetic field or to cool the device below (or heat it above) room temperature to obtain EPIC. Examples of suitable CMR perovskites include Pr(1-x)Ca(x)MnO3, La(1-x)S-r(x)MnO3,and Nb(1-x)Ca(x)MnO3. Figure 2 is a block diagram showing an EPIC capacitor connected to a circuit that can vary the capacitance, measure the capacitance, and/or measure the resistance of the capacitor.

Shangqing, Liu↗

Thickness scaling and ferroelectric switching in wurtzite structure zinc magnesium oxide thin films

This study reports the thickness scaling of sputtered ferroelectric Zn 0.61 Mg 0.39 O (ZMO) thin films down to 43 nm. Encapsulated IrO 2 /ZMO/Ir capacitors exhibited switchable polarizations exceeding 50 μC cm −2 and coercive fields that increased from 3.9 to 4.4 MV cm −1 as the thickness decreased. Switching kinetics are best described by the simultaneous non-linear nucleation and the growth model. Bimodal switching is prevalent at low thicknesses, with the fastest switching times measured to be approximately 400 ns. Device encapsulation made ZMO switching kinetics more abrupt, potentially due to changes in the concentration of atmosphere-induced defects such as hydroxides. These results demonstrate stable ferroelectricity and sub-microsecond switching in sub-50 nm wurtzite ZMO, highlighting its potential as a low-voltage ferroelectric for integrated nonvolatile memory applications.

36 MATERIALS SCIENCE↗

Xyce Parallel Electronic Simulator Users' Guide (Version 7.2)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandias needs, including some radiation-aware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase - a message passing parallel implementation - which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗