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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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When performing a single event effect (SEE) test during a test campaign, flexibility and out of the box thinking is often required for unexpected and unplanned events.
NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of Trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.
NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.
We present updates to the conventional methodology of triple modular redundancy (TMR) insertion as it pertains to clock domain crossings (CDCs). Three types of TMR schemes and their suggested corresponding CDC revisions are discussed.
This presentation describes the accelerating use of Commercial off the Shelf (COTS) parts in space applications. Component reliability and threats in the context of the mission, environment, application, and lifetime. Provides overview of traditional approaches applied to COTS parts in flight applications, and shows challenges and potential paths forward for COTS systems in flight applications it's all about data!
This is an independent investigation that evaluates the single event destructive and transient susceptibility of the Xilinx Kintex-UltraScale device. Design/Device susceptibility is determined by monitoring the device under test (DUT) for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) is monitored throughout heavy-ion testing by examining device current. This device does not have embedded mitigation. Hence, user implemented mitigation is investigated using Synopsys mitigation tools.
We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data to improve system survivability prediction.
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This report presents 2019 LBNL SEE data and compares previous Texas A&M data to LBNL SEE DUT responses.
This paper provides an overview of the communications system that is being developed as part of the Micro Communications and Avionics Systems (MCAS).
The National Aeronautics and Space Administration (NASA) at Glenn Research Center (GRC) has developed an optical communications transmitter and receiver using Commercial-off-the-shelf (COTS) components. The goal of this project is to become fully compliant with Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard. The receive modem’s decoder has been modified using shift registers to enable the decoding of higher data rate pulse-position modulation (PPM) 4 and PPM-8 signals. PPM-4 and PPM-8 is then verified by comparing the codeword error rate (CWER) of a hardware implementation to a software simulation. The changes show the capability to decode PPM-4 and PPM-8 for a single decoder. This memorandum details the changes made, the performance achieved with the changes, and necessary future work.
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Some Industrial Control Systems (ICS) networks are based on protocols such as Serial and Industrial Ethernet. These protocols currently have no existing cybersecurity monitoring tools, leaving a large gap in the cyber defense of critical infrastructure. In order to analyze such ICS traffic, it is first necessary to implement methods of capturing the ICS data. Whereas traditional methods of analyzing data would use microprocessors, the nature of high-speed analog data can be difficult to implement on such a versatile processor, as they are rather inefficient for doing a single task. Whereas Field Programmable Gate Arrays (FPGAs) provide an adequate tool in analyzing high speed data, as despite the lack of program versatility, Programmable Logic can implement a solution with minimal clock cycles, allowing time for each new packet of data to be captured before a new data sample is taken.
Slides providing an overview of microelectronics cybersecurity and research concepts at INL.