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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 919 records · Page 51
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

TPSAS-NF1676L-9990-DND

PVS (Prototype Veri cation System)1 is an interactive environment for the specification and verification of systems. PVS provides a strongly typed specification language, which is based on Higher-Order Logic. The type system of PVS supports: sub-typing, dependent-types, abstract data types, parametric types, records, unions, and tuples. The PVS theorem prover includes decision procedures for a variety of theories such as linear arithmetic, propositional logic, and temporal logic. This seminar will provide a gentle introduction to the basic and advanced features of PVS, including: theory interpretations, real number proving, batch proving, rapid prototyping, and strategy development. All these features are illustrated with simple examples and exercises.

César Muñoz↗
NASA NTRS2018

Efficient Runtime Verification of First-Order Temporal Properties

Runtime verification allows monitoring the execution of a system against a temporal property, raising an alarm if the property is violated. In this paper we present a theory and system for runtime verification of a first-order past time linear temporal logic. The first-order nature of the logic allows a monitor to reason about events with data elements. While runtime verification of propositional temporal logic requires only a fixed amount of memory, the first-order variant has to deal with a number of data values potentially growing unbounded in the length of the execution trace. This requires special compactness considerations in order to allow checking very long executions. In previous work we presented an efficient use of BDDs for such first-order runtime verification, implemented in the tool DEJAVU. We first summarize this previous work. Subsequently, we look at the new problem of dynamically identifying when data observed in the past are no longer needed, allowing to reclaim the data elements used to represent them. We also study the problem of adding relations over data values. Finally, we present parts of the implementation, including a new concept of user defined property macros.

Peled, Doron↗
NASA NTRSDate not supplied

Minimum-Violation Traffic Management for Urban Air Mobility

Urban air mobility (UAM) refers to air transportation services in and over an urban area and has the potential to revolutionize mobility solutions. However, due to the projected scale of operations, current air traffic management (ATM) techniques are not viable. Increasingly autonomous systems are a pathway to accelerate the realization of UAM operations but must be fielded safely and efficiently. The heavily regulated, safety critical nature of aviation may lead to multiple, competing safety constraints that can be traded off based on the operational context. In this paper, we design a framework which allows for the scalable planning of a UAM ATM system. We formalize safety oriented constraints derived from FAA regulations by encoding them as temporal logic formulae. We then propose a method for UAM ATM that is both scalable and minimally violates the temporal logic constraints. Numerical results show that the runtime for our proposed algorithm is suitable for very large problems and is backed by theoretical guarantees of correctness with respect to given temporal logic constraints.

Urban Air Mobility↗
NASA NTRSDate not supplied

Applying Formal Methods to Safety-Critical Systems

How do you know a proof is correct? Traditionally, mathematical proofs are socially verified – at least one human, following a set of implicit rules of natural language and logic, determines if the proof is believable. If the proof becomes overly tedious and/or is essential to some safety- or mission-critical application, it becomes necessary to determine the soundness to a higher standard. 'Formal methods' refer to mathematically rigorous techniques and tools that enable specification, design, and verification of hardware and software systems. The specification used in formal methods are statements in a mathematical logic while the formal verifications are deductions in that logic. Formal methods can be difficult or time/resource intensive, but offer a higher level of assurance than standard verification through testing or handwritten proofs. This talk will introduce formal methods, motivated by applications of interest to NASA, including uncrewed aircraft operations in the national airspace, urban air environments, and wildfire areas. The audience will be given a crash course in mechanically verified proofs in the Prototype Verification System (PVS), an interactive theorem prover.

Formal Methods↗
NASA NTRSDate not supplied

Floquet Codes on Non-Trivalent Lattices

Floquet codes are a novel form of quantum error correcting codes, where the logical degrees of freedom appear in a dynamical form. The first example of such a code was constructed by Hastings and Haah on a honeycomb lattice. Specifically, they showed how to Floquetify the Kitaev honeycomb model, which when viewed as a subsystem code, encodes no logical qubits. However, by choosing a particular measurement schedule of the check operators, this model leads to dynamically encoded logical qubits. Since this initial work, several examples of Floquet codes have been constructed, mainly on trivalent lattices. Here, we report progress on understanding when such codes can be implemented on lattices of different connectivities.

Muhammad Sohaib Alam↗
DOE OSTI2020

Quantum self-authenticating timing system

An improved method of distributing timing information is provided. The method includes transmitting encrypted timing signals from two or more beacons at different locations. The encrypted timing signals are transmitted at regular intervals and are received by a receiver. The receiver then performs a logic operation on the encrypted timing signals and validates, based on the logic operation, the authenticity of the timing signals. The logic operation also results in a decrypted message from the beacons, which can contain additional information, for example, data to be sent back to the beacons to verify receipt.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units

A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Method and apparatus for virtualizing the micro-op cache

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Kalamatianos, John↗
DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗
DOE OSTI2022

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

Yalavarti, Adithya↗
DOE OSTI2022

Compressing micro-operations in scheduler entries in a processor

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

Boyer, Michael W.↗
DOE OSTI2023

Method and apparatus for virtualizing the micro-op cache

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Kalamatianos, John↗
DOE OSTI2023

Systems and methods for verification and authentication of remote sensing imagery

A system for generating and authenticating remote sensing imagery includes a remote sensing platform. The remote sensing platform includes an imaging sensor and a hardware logic device that is directly coupled to the imaging sensor. The hardware logic device receives image data from the imaging sensor and generates a cryptographic signature based upon the image data. The hardware logic device outputs a signed image that includes the image data and the cryptographic signature. A computing device operated by a downstream user receives the signed image and can determine whether the image data has been modified from its original content based upon the cryptographic signature.

Crosby, Sean Michael↗
DOE OSTI2023

Trapped-ion entangling gates with bichromatic pair of microwave fields and magnetic field gradient

A trapped-ion quantum logic gate and a method of operating the trapped-ion quantum logic gate are provided. The trapped-ion quantum logic gate includes at least one ion having two internal states and forming a qubit having a qubit transition frequency ω 0 0, a magnetic field gradient, and two microwave fields. Each of the two microwave fields has a respective frequency that is detuned from the qubit transition frequency ω 0 by frequency difference δ. The at least one ion has a Rabi frequency Ω μ due to the two microwave fields and a Rabi frequency Ω g due to the magnetic field gradient. The method includes applying the magnetic field gradient and the two microwave fields to the at least one ion such that a quantity Ω g /δ is in a range between zero and 5×10 −2 .

Sutherland, Robert Tyler↗
DOE OSTI2022

Multi-Pressure Rail System Design with Variable Pressure Control Strategy

This paper presents the design and the control method of a Multiple Pressure Rail system (MPR) with a variable pressure control logic that allows minimization of throttling loss, therefore, increasing the overall fluid power actuation efficiency. An MPR system allows controlling hydraulic actuators with a pressure control logic, as opposed to traditional flow control logics which are well established in mobile applications. A proper setting of the number of pressure rails and the pressure level in each rail permits optimizing the system efficiency of an MPR solution. MPR systems have been recently proposed with different purposes, but seldom adopt variable pressure control strategies to manage the pressure variations in the rails. Moreover, the related past work attempts to maximize the energy recovery during overrunning load conditions. This paper, instead, addresses the case of an MPR system that handles a multitude of hydraulic functions without significant overrunning loads, as it occurs in many mobile applications such as in agriculture. The paper first presents the design alternatives considered for the MPR system, including the supply, the control valves, and the controller. Second, a dedicated test rig is developed to support experimental activities and validations of a lumped parameter model developed within this research to develop the MPR control strategy. The results describe the operating features of the proposed MPR solution. By considering the case of a traditional LS system, the paper results also show how system efficiency can be highly improved, with energy savings in the order of 49%

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗
DOE OSTI2025

Control System Upgrade for Battery State-of-Charge Indications

The Advanced Test Reactor (ATR) Complex at Idaho National Laboratory (INL) relies on Battery Backed Power (BBP) systems and Uninterruptible Power Supplies (UPS) to ensure continuous power supply to critical components. This project aims to enhance the reliability and functionality of the battery monitoring and control systems by updating the State-of-Charge (SOC) system, Programmable Logic Controller (PLC), and Human-Machine Interface (HMI) for the nuclear safety-related battery banks. The current system, while functional, has areas for improvement, particularly in recharging calculations and alarm functions. The project objectives include developing flow charts, programming the new PLC and HMI, conducting bench tests, and updating design documentation. Additionally, the project ensures compliance with safety standards, develops training materials, creates comprehensive documentation, and integrates seamlessly with existing ATR infrastructure. The new SOC system is designed to be scalable for future upgrades, improve efficiency, enhance data accuracy, implement redundancy features, and achieve project goals within budget constraints while considering environmental impact. The methodology involved familiarizing with BBP and UPS systems, collecting current readings, rescaling signals, learning ladder logic, and updating the HMI. The transition from SLC 5/03 PLC using RS Logix 500 to CompactLogix 5380 using Studio 5000 was a key step. Despite challenges in transferring outdated PLC ladder logic and HMI code, starting from scratch led to a more accurate and efficient monitoring system, contributing to improved safety and operational efficiency. The project is currently awaiting approval of the Engineering Calculation and Analysis Report (ECAR) before implementation.

42 - ENGINEERING↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗