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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Design and Test of Xilinx Embedded ECC for MicroBlaze Processors
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Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment
This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.
Scalable quantum processor noise characterization
Measurement fidelity matrices (MFMs) (also called error kernels) are a natural way to characterize state preparation and measurement errors in near-term quantum hardware. They can be employed in post processing to mitigate errors and substantially increase the effective accuracy of quantum hardware. However, the feasibility of using MFMs is currently limited as the experimental cost of determining the MFM for a device grows exponentially with the number of qubits. In this work we present a scalable way to construct approximate MFMs for many-qubit devices based on cumulant expansions. Our method can also be used to characterize various types of correlation error.
Compute Overlap Stall (COS): Predicting Performance of Power Management for Shared Memory Codes When Throttling Processors, Memory, and Thread Concurrency
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Physical vapor deposition simulator by graphical processor unit ray casting
This paper presents fast, accurate software for modeling physical vapor deposition systems over irregular surfaces. The model is implemented using graphics processing unit (GPU) ray casting. Applied models are viewed as a cross section of the area of interest. Given evaporation rate, time, and angular profiles in a vacuum system, an iterative time-step approach for calculating deposition profiles is calculated in the GPU architecture following a ballistic modeling approach. Thin-film technologies for the electronics industry will require evaporations on complex surfaces. Depending on the nature of the surface, a uniform thin film across the topology is wanted for various device parameters. The ray casting method is tested against various profiles. The code is freely distributed on GitHub (see https://github.com/adam-r-thomas/PVDS).
Quantum error mitigations for quantum approximate optimization algorithms on IBM quantum processors
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COS: A Parallel Performance Model for Dynamic Variations in Processor Speed, Memory Speed, and Thread Concurrency
Abstract not provided
LMStr: An On-Chip Shared Hardware Controlled Scratchpad Memory for Multicore Processors.
Abstract not provided.
TISCC: A Surface Code Compiler and Resource Estimator for Trapped-Ion Processors
We introduce the Trapped-Ion Surface Code Compiler (TISCC), a software tool that generates circuits for a universal set of surface code patch operations in terms of a native trapped-ion gate set. To accomplish this, TISCC manages an internal representation of a trapped-ion system where a repeating pattern of trapping zones and junctions is arranged in an arbitrarily large rectangular grid. Surface code operations are compiled by instantiating surface code patches on the grid and using methods to generate transversal operations over data qubits, rounds of error correction over stabilizer plaquettes, and/or lattice surgery operations between neighboring patches. Beyond the implementation of a basic surface code instruction set, TISCC contains corner movement functionality and a patch translation that is implemented using ion movement alone. Except in the latter case, all TISCC functionality is extensible to alternative grid-like hardware architectures. TISCC output has been verified using the Oak Ridge Quasi-Clifford Simulator (ORQCS).
An efficient MPI/OpenMP parallelization of the Hartree–Fock–Roothaan method for the first generation of Intel® Xeon Phi™ processor architecture
The Hartree-Fock (HF) method in the quantum chemistry package GAMESS represents one of the most irregular algorithms in computation today. Major steps in the calculation are the irregular computation of electron repulsion integrals (ERIs) and the building of the Fock matrix. These are the central components of the main Self Consistent Field (SCF) loop, the key hotspot in Electronic Structure (ES) codes. By threading the MPI ranks in the official release of the GAMESS code, we not only speed up the main SCF loop (4x to 6x for large systems), but also achieve a significant (>2x) reduction in the overall memory footprint. These improvements are a direct consequence of memory access optimizations within the MPI ranks. We benchmark our implementation against the official release of the GAMESS code on the Intel R Xeon PhiTM supercomputer. Here, scaling numbers are reported on up to 7,680 cores on Intel Xeon Phi coprocessors.
An IGES and OFF to MCNP geometry processor
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Aluminum Nitride Based MEMS IF Filter Array for Analog Spectral Processors
The purpose of this project was to enable new levels of performance in radio frequency systems, such as adaptability, size and stability, based on aluminum nitride microresonator technology. Early in the project, in 2008, Sandia developed arrays of filters for realizing high scan rate spectrum analyzers at 20 MHz and Rockwell Collins demonstrated a high scan rate spectrum analyzer leveraging this technology in 2009. The filter arrays, because of the transduction physics, demonstrated massively reduced size, loss and impedance compared to existing filter technologies. These device level benefits translated to reduced size and power for the spectrum analyzers at the system level.
Data Processor 3 QASPR Project
The following discussion contains a high-level description of methods used to implement software for data processing. It describes the required directory structures and file handling required to use Excel's Visual Basic for Applications programming language and how to identify shot, test and capture types to appropriately process data. It also describes how to interface with the software.
HALEU Decontamination Investigations for EBR-II Recovered Uranium. HALEU Drip Casting Results in the Fuel Conditioning Facility Cathode Processor
Many of the new advanced reactor designs being proposed by the nuclear private sector require uranium fuel enriched between 5 and 20%, otherwise known as High Assay Low Enriched Uranium (HALEU), to support their designs. There are currently no commercial facilities based in the United States which have the capability to produce this material, and as a result the nuclear industry has requested support from the Department of Energy (DOE) to meet this need. One approach being considered by DOE to respond to this demand is to recover highly enriched uranium from used nuclear fuels and downblend it to enrichments less than 20 % U-235. DOE’s past research related to liquid metal fast breeder reactors resulted in the irradiation of more than 3 metric tons (MT) of nuclear fuel composed of highly enriched metallic uranium which resides at the Idaho National Laboratory (INL). This inventory of used nuclear fuel is currently being conditioned using an electrometallurgical treatment process (EMT) to facilitate its eventual disposition to a geologic repository. As part of this treatment process, the highly enriched component of this used fuel is separated, recovered, downblended to <20% U-235, and stored as a metallic uranium ingot. The majority of this fuel was irradiated in the Experimental Breeder Reactor II (EBR-II) over the course of its 30 years of operation. This sodium cooled fast reactor utilized a core composed of highly enriched, sodium-bonded, metallic fuel to sustain or “drive” the reactor. This EBR-II driver fuel is currently being treated for sodium neutralization in the Fuel Conditioning Facility (FCF) at the Materials and Fuels Complex (MFC) and the metallic uranium recovered as a component of this process has been proposed as a potential source of supply of high assay low enriched uranium. The irradiation of the metallic uranium fuel results in the creation of fission products and some minor actinides which are not compatible with many reuse scenario’s, and introduces significant challenges associated with fabrication of new fuel elements using this material. However, it is believed that the current EMT process can be slightly enhanced to address these concerns and result in the recovery of a product that can be considered as a source of supply for HALEU applications. Based on this, DOE requested the INL research methods to enhance the EMT process to produce a recovered uranium material that has a lower contaminant level and lower radiological dose rate and could be utilized in glovebox based fuel fabrication scenarios. The report that follows documents the progress toward meeting this goal.