Space Data Storage Systems and Technologies
A central aspect of most space missions is the acquisition from space of unique mission-specific data and the subsequent return of these data to Earth.
storage ranging from magnetic tape to solid-state ↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012
The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.
Irom, Farokh↗
Radiation tests of highly scaled, high-density, commercial, nonvolatile NAND flash memories— update 2012
The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.
Allen, Gregory R.↗
Soft error-mitigating semiconductor design system and associated methods
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.
Miryala, Sandeep↗
Soft error-mitigating semiconductor design system and associated methods
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.
Miryala, Sandeep↗
GAHLS: an optimized graph analytics based high level synthesis framework
The urgent need for low latency, high-compute and low power on-board intelligence in autonomous systems, cyber-physical systems, robotics, edge computing, evolvable computing, and complex data science calls for determining the optimal amount and type of specialized hardware together with reconfigurability capabilities. With these goals in mind, we propose a novel comprehensive graph analytics based high level synthesis (GAHLS) framework that efficiently analyzes complex high level programs through a combined compiler-based approach and graph theoretic optimization and synthesizes them into message passing domain-specific accelerators. This GAHLS framework first constructs a compiler-assisted dependency graph (CaDG) from low level virtual machine (LLVM) intermediate representation (IR) of high level programs and converts it into a hardware friendly description representation. Next, the GAHLS framework performs a memory design space exploration while account for the identified computational properties from the CaDG and optimizing the system performance for higher bandwidth. The GAHLS framework also performs a robust optimization to identify the CaDG subgraphs with similar computational structures and aggregate them into intelligent processing clusters in order to optimize the usage of underlying hardware resources. Finally, the GAHLS framework synthesizes this compressed specialized CaDG into processing elements while optimizing the system performance and area metrics. Evaluations of the GAHLS framework on several real-life applications (e.g., deep learning, brain machine interfaces) demonstrate that it provides 14.27× performance improvements compared to state-of-the-art approaches such as LegUp 6.2.
97 MATHEMATICS AND COMPUTING↗
On-the-fly response function generation method for composite coarse mesh
The hybrid stochastic deterministic transport code COMET, based on the incident response expansion theory, is used to model reactor cores with high fidelity and formidable computational speed. COMET models a reactor core using a library of incident flux response expansion coefficients that are pre computed for all the unique lattice cells (e.g., fuel assemblies, reflector blocks, etc.) in the core. In order to further improve its computational efficiency in pre-calculating the response library a new response function generation method is developed to compute the response functions for the composite coarse meshes made of a smaller set of unique lattices on the fly within the COMET's deterministic transport core sweep. The efficiency is achieved by eliminating a number of unique lattices that can be made up from the reduced set of unique meshes on the fly. The numerical process consists of the following steps. First, the boundary condition on composite coarse mesh boundaries is projected onto the expansion basis to compute the incident flux moments on external surfaces of all the basic (reduced set of unique) coarse meshes. Secondly, the deterministic sweeping solver in COMET is used to converge on the outgoing/incoming flux expansion moments crossing interfaces between the basic coarse meshes. Thirdly, the response functions for the composite coarse meshes are constructed as a superposition on the fly. The new response function generation method was tested on 88 composite coarse meshes consisting of CANDU fuel bundles and moderator blocks. It was found that response functions generated by the new method agree very well with those generated by direct Monte Carlo calculations. The average and maximum relative differences in the surface-to-surface response coefficients computed by the two methods are 0.10% and 0.20%, respectively. Similarly, the average and maximum relative differences in the response fission densities are 0.13% and 0.43%, respectively. These discrepancies are within one standard deviation of the stochastic uncertainties. The new method is five times faster than the original direct Monte Carlo method. The size of the response function library for the new method is five times smaller than that for the original method, leading to significantly less requirement for the computer hard drive space and memory. (authors)
21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
The ninth Dr. Albert Plesman memorial lecture: The Future of Space Flight
The history of space flight is reviewed and major NASA programs (Mercury, Gemini, Apollo, Skylab, Apollo-Soyuz, Science and Applications, Space Shuttle, Space Station) are summarized. Developments into the early 21st century are predicted.
Moore, J. W.↗
A Succinct Naming Convention for Lengthy Hexadecimal Numbers
Engineers, computer scientists, mathematicians and others must often deal with lengthy hexadecimal numbers. As memory requirements for software increase, the associated memory address space for systems necessitates the use of longer and longer strings of hexadecimal characters to describe a given number. For example, the address space of some digital signal processors (DSP's) now ranges in the billions of words, requiring eight hexadecimal characters for many of the addresses. This technical memorandum proposes a simple grouping scheme for more clearly representing lengthy hexadecimal numbers in written material, as well as a "code" for naming and more quickly verbalizing such numbers. This should facilitate communications among colleagues in engineering and related fields, and aid in comprehension and temporary memorization of important hexadecimal numbers during design work.
Grant, Michael S.↗
Heavy Ion Testing of Freescale Nano-Crystal Nonvolatile Memory
This viewgraph presentation describes radiation tests of nanocrystal (NC) memory for space systems. A nanocrystal test chip was bombarded by heavy ions from a cyclotron.
Oldham, T. R.↗
Radiation-Hardened Solid-State Drive
A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.
Sheldon, Douglas J.↗
A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors
Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.
Nguyen, Kayla↗
Overview of Non-Volatile Memory Packaging Needs and Approaches for Space Based Systems
Structure and Evolution of the Universe; Explain structure of the Universe and forecast our cosmic future.
Space↗
Satellite Test of Radiation Impact on Ramtron 512K FRAM
The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite. The test consists of writing and reading data with a ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is send to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test will be one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The memory devices being tested is a Ramtron Inc. 512K memory device. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.
MacLeod, Todd C.↗
Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite
The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.
MacLeond, Todd C.↗
Frequency and time multiplexing for multiphoton state generation
One of the primary challenges with photonic quantum information processing is that single-photon states are created and heralded probabilistically, rather than being created on demand. One solution to this problem is multiplexing , which is attempting probabilistic generation of a single photon at multiple locations, times, or frequencies, and switching one successfully generated photon into an output mode. Motivated by the development of frequency-based photonic quantum information processing, we consider multiplexing using frequency and time as our options to use to get many photon generation opportunities. We devise an approach for generating multiphoton states, with photons populating multiple frequency modes in the same spatiotemporal mode. This method uses a variable-length optical delays to manipulate the temporal mode of the photons, and spaced fiber Bragg grating (FBG) reflectors to jointly manipulate the frequency and temporal modes of the photons. Experimental progress toward implementing this multiplexing scheme is proceeding along 2 fronts, each with different ways to achieve the variable-length optical delay. First, we will implement this scheme using a free-space optical quantum memory with multiple discretely adjustable free-space delays. For this implementation method, I calculate multiphoton generation rates, accounting for loss, that are realistically achievable with commercially available hardware. This work will appear in a theory paper, currently in preparation. Second, we will implement this multiplexing scheme in an integrated manner: the variable-length optical delay will happen on-chip using a long-lifetime Q-switchable Fabry-Perot cavity. The joint manipulation of the frequency and temporal modes of the photons will still happen off-chip in fiber with FBG reflectors. I report on experimental progress in constructing integrated Q-switchable Fabry-Perot cavities.
97 MATHEMATICS AND COMPUTING↗
Accuracy of saccades to remembered targets as a function of body orientation in space
A vertical asymmetry in memory-guided saccadic eye movements has been previously demonstrated in humans and in rhesus monkeys. In the upright orientation, saccades generally land several degrees above the target. The origin of this asymmetry has remained unknown. In this study, we investigated whether the asymmetry in memory saccades is dependent on body orientation in space. Thus animals performed memory saccades in four different body orientations: upright, left-side-down (LSD), right-side-down (RSD), and supine. Data in all three rhesus monkeys confirm previous observations regarding a significant upward vertical asymmetry. Saccade errors made from LSD and RSD postures were partitioned into components made along the axis of gravity and along the vertical body axis. Up/down asymmetry persisted only in body coordinates but not in gravity coordinates. However, this asymmetry was generally reduced in tilted positions. Therefore the upward bias seen in memory saccades is egocentric although orientation in space might play a modulatory role.
NASA Discipline Neuroscience↗
Extending the Memory of Microcomputers
Memory increased while retaining real-time capabilities. Extra memory capacity added to microprocessor without increasing memory address length and special transfer instructions by dedicating block of space in main memory to hold addresses of locations in extra memory.
Wiker, G. A.↗