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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Integrated silicon optical amplifier with reduced residual pump

An optical amplifier device employing a Mach-Zehnder Interferometer (MZI) that reduces the amount of residual pump power in the optical output of the amplifier is disclosed. The MZI amplifier employs two geometrically linear optical amplifier arms or two multi-spatial-mode racetrack optical amplifiers to amplify a signal with a pumping beam, with the signal output port having extremely low levels of residual pump power. The MZI optical amplifier is a silicon photonic integrated circuit, with all optical amplifiers, couplers, phase shifters, and optical attenuators formed of silicon photonic integrated circuit elements. The MZI optical amplifier may include one, two, or three MZI stages, and multiple MZI optical amplifiers may be used in parallel or sequentially to achieve higher overall signal gain or power. The MZI optical amplifier may employ Brillouin-scattering-based amplifiers, Raman-based integrated waveguide optical amplifiers, or Erbium-doped integrated waveguide optical amplifiers.

Lentine, Anthony L.↗
DOE OSTI2024

Tunable quantum emitters on large-scale foundry silicon photonics

Abstract Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries.

Larocque, Hugo (ORCID:000900095849780X)↗
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2026

Nanophotonic waveguide chip-to-world beam scanning

A seamless chip-to-world photonic interface enables broad advancements in optical ranging, display, communication, computation and quantum information science. The ideal solution enables two-dimensional scanning of a diffraction-limited beam from anywhere on a photonic integrated circuit to a large number of resolvable spots. Current beam-scanning technologies are limited by a fundamental trade-off: photonic-integrated-circuits with diffractive optics offer scalability but have poor mode quality, whereas inertially limited micromechanical scanners provide high-quality beams but lack scalable integration. Here we report a photonic ski-jump—a nanoscale waveguide monolithically integrated on a piezoelectric cantilever—to overcome these limitations. It passively curls ~90° out-of-plane within a less-than-0.1 mm 2 footprint, emits a submicrometre, broadband diffraction-limited beam, and exhibits kilohertz-rate mechanical resonances with quality factors of over 10,000. Fabricated in a volume complementary metal–oxide–semiconductor (CMOS) foundry, our device enables scalable two-dimensional beam scanning. Driven on-resonance at CMOS-level voltages, it achieves a footprint-adjusted spot rate of 68.6 mega spots s –1 mm–², exceeding state-of-the-art micro-electro-mechanical systems mirrors by more than 50-fold, which is sufficient for one million pixels at 100 Hz from an approximately 1.5 mm diameter footprint. We demonstrate full-colour image and video projection, and single-photon initialization and readout from silicon vacancy centres in diamond. Finally, by demonstrating uniformity across a 64 ski-jump array, we establish a pathway to achieving greater than one gigaspot resolution at kilohertz rates within a sub-5-cm-diameter footprint, creating a seamless optical pipeline between integrated photonic processors and the free-space world.

Displays↗
DOE OSTI2022

Low voltage AC electroluminescence in silicon MOS capacitors

Low power silicon based light source and detector are attractive for on-chip photonic circuits given their ease of process integration. However, conventional silicon light emitting diodes emit photons with energies near the band edge where the corresponding silicon photodetectors lack responsivity. On the other hand, previously reported hot carrier electroluminescent silicon devices utilizing a reverse biased diode require high operating voltages. Here, we investigate hot carrier electroluminescence in silicon metal–oxide–semiconductor capacitors operating under transient voltage conditions. Further, during each voltage transient, large energy band bending is created at the edge of the source contact, much larger than what is achievable at a steady state. As a result, electrons and holes are injected efficiently from a single source contact into the silicon channel at the corresponding voltage transient, where they subsequently undergo impact ionization and phonon-assisted interband recombination. Notably, we show low voltage operation down to 2.8 V by using a 20 nm thick high-κ gate dielectric. We show further voltage scaling is possible by reducing the gate dielectric thickness, thus presenting a low voltage platform for silicon optoelectronic integrated circuits.

42 ENGINEERING↗
DOE OSTI2024

Radio Frequency Properties of a 3D Printed Klystron Circuit

The manufacturing of active RF devices like klystrons is dominated by expensive and time-consuming cycles of machining and brazing. In this article, we characterize the RF properties of X-band klystron cavities and an integrated circuit manufactured with a novel additive manufacturing process. Parts are 3D printed in 316 L stainless steel with direct metal laser sintering, electroplated in copper, and brazed in one simple braze cycle. Stand-alone test cavities and integrated circuit cavities were measured throughout the manufacturing process. The un-tuned cavity frequency varies by less than 5% of the intended frequency, and Q factors reach above 1200. A tuning study was performed, and unoptimized tuning pins achieved a tuning range of 138 MHz without compromising Q. Klystron system performance was simulated with as-built cavity parameters and realistic tuning. Together, these results show promise that this process can be used to cheaply and quickly manufacture a new generation of highly integrated high power vacuum devices.

3D printing↗
DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗
DOE OSTI2022

Packet router with virtual channel hop buffer control

An integrated circuit includes a network on chip (NOC) that includes a plurality of processing elements and a plurality of NOC nodes, interconnected to the plurality of processing elements. The integrated circuit includes logic that is configured to: increment by one, a virtual channel identifier to produce an incremented destination VC identifier, the virtual channel (VC) identifier associated with at least portion of a packet stored in at least one virtual channel buffer; determine that a destination virtual channel buffer corresponding to the incremented destination VC identifier in a destination NOC node in the NOC is available to store the portion of the packet; and in response to the determination, send the portion of the packet and the incremented destination VC identifier to the destination NOC node.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Piezoelectric deformable photonic devices

A CMOS-compatible actuator platform for implementing phase, amplitude, and frequency modulation in silicon nitride photonic integrated circuits via piezo-optomechanical coupling using tightly mechanically coupled aluminum nitride actuators is disclosed. The platform, which may be fabricated in a CMOS foundry, enables scalable active photonic integrated circuits for visible wavelengths, and the piezoelectric actuation functions without performance degradation down to cryogenic operating temperatures. A number of devices are possible, including ring modulator devices, phase shifter devices, Mach-Zehnder interferometer devices, directional coupler devices (including tunable directional coupler devices), and acousto-optic modulator and frequency shifter devices, each of which can employ the same AlN actuator platform. As all of these devices can be built on the same AlN actuator platform, numerous optical functions can be implemented on a single die.

Eichenfield, Matt↗
DOE OSTI2020

Novel spectral-shaping building block: a narrowband Mach–Zehnder interferometer

We present an experimental demonstration of notch filters with arbitrary center wavelengths capable of tunable analog output power values varying between full extinction of 15 and 0 dB. Each filter is composed of highly modular apodized four-port Bragg add/drop filters to reduce the crosstalk between concatenated devices. The constructed photonic integrated circuit experimentally demonstrates spectra shaping using four independent notch filters. Each notch filter supports a bandwidth of ∼ 2 nm and is shown to be suitable for realization of programmable photonic integrated circuits.

Davis, Jordan A. (ORCID:0000000343483295)↗
DOE OSTI2020

Wavefront detector

A wavefront sensor system suitable for integration into an integrated circuit light detector may provide for wave angle sensors having varying functional relationships between the wave angle and signal to provide improved dynamic range. These wave angle sensors may be combined with integrated circuit phase angle sensors for a more complete analysis of the waveform.

42 ENGINEERING↗
DOE OSTI2021

Wavefront detector

A wavefront sensor system suitable for integration into an integrated circuit light detector may provide for wave angle sensors having varying functional relationships between the wave angle and signal to provide improved dynamic range. These wave angle sensors may be combined with integrated circuit phase angle sensors for a more complete analysis of the waveform.

Yu, Zongfu↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
DOE OSTI2021

Routing flits in a network-on-chip based on operating states of routers

A system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers keeps a record of operating states of some or all of the multiple routers and corresponding communication links. The given router then routes flits to destination nodes via one or more other routers of the multiple routers based at least in part on the operating states of the some or all of the multiple routers and the corresponding communication links.

Bharadwaj, Srikant↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗