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DOE OSTI · 1924931

Packet router with virtual channel hop buffer control

Bharadwaj, Vedula Venkata Srikant
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Abstract

An integrated circuit includes a network on chip (NOC) that includes a plurality of processing elements and a plurality of NOC nodes, interconnected to the plurality of processing elements. The integrated circuit includes logic that is configured to: increment by one, a virtual channel identifier to produce an incremented destination VC identifier, the virtual channel (VC) identifier associated with at least portion of a packet stored in at least one virtual channel buffer; determine that a destination virtual channel buffer corresponding to the incremented destination VC identifier in a destination NOC node in the NOC is available to store the portion of the packet; and in response to the determination, send the portion of the packet and the incremented destination VC identifier to the destination NOC node.

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Bharadwaj, Vedula Venkata Srikant. 2022-07-26. Packet router with virtual channel hop buffer control. https://www.osti.gov/biblio/1924931

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