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At least 91 records · Page 5

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗

Fundamental Hardware Design in PVS

The development of Programmable Logic Devices (PLDs) has introduced programming as a primary tool in the development of digital circuits. This work attempts to create a generic verification environment in which designs can be specified and verified using the Prototype Verification System (PVS). This is accomplished by providing library support for general hardware constructs. The environment is intended for use with any PLD and any PLD programming language. The goal of the environment is to allow the easy translation of digital designs to PVS and provide sufficient support to make verification possible without a great deal of effort.

Leathrum, James F., Jr.↗

Electronics Demonstrated for Low- Temperature Operation

The operation of electronic systems at cryogenic temperatures is anticipated for many NASA spacecraft, such as planetary explorers and deep space probes. For example, an unheated interplanetary probe launched to explore the rings of Saturn would experience an average temperature near Saturn of about 183 C. Electronics capable of low-temperature operation in the harsh deep space environment also would help improve circuit performance, increase system efficiency, and reduce payload development and launch costs. An ongoing research and development program on low-temperature electronics at the NASA Glenn Research Center at Lewis Field is focusing on the design of efficient power systems that can survive and exploit the advantages of low-temperature environments. The targeted systems, which are mission driven, include converters, inverters, controls, digital circuits, and special-purpose circuits. Initial development efforts successfully demonstrated the low-temperature operation and cold-restart of several direct-current/direct-current (dc/dc) converters based on different types of circuit design, some with superconducting inductors. The table lists some of these dc/dc converters with their properties, and the photograph shows a high-voltage, high-power dc/dc converter designed for an ion propulsion system for low-temperature operation. The development efforts of advanced electronic systems and the supporting technologies for low-temperature operation are being carried out in-house and through collaboration with other Government agencies, industry, and academia. The Low Temperature Electronics Program supports missions and development programs at NASA s Jet Propulsion Laboratory and Goddard Space Flight Center. The developed technologies will be transferred to commercial end users for applications such as satellite infrared sensors and medical diagnostic equipment.

Patterson, Richard L.↗

JavaGenes: Evolving Graphs with Crossover

Genetic algorithms usually use string or tree representations. We have developed a novel crossover operator for a directed and undirected graph representation, and used this operator to evolve molecules and circuits. Unlike strings or trees, a single point in the representation cannot divide every possible graph into two parts, because graphs may contain cycles. Thus, the crossover operator is non-trivial. A steady-state, tournament selection genetic algorithm code (JavaGenes) was written to implement and test the graph crossover operator. All runs were executed by cycle-scavagging on networked workstations using the Condor batch processing system. The JavaGenes code has evolved pharmaceutical drug molecules and simple digital circuits. Results to date suggest that JavaGenes can evolve moderate sized drug molecules and very small circuits in reasonable time. The algorithm has greater difficulty with somewhat larger circuits, suggesting that directed graphs (circuits) are more difficult to evolve than undirected graphs (molecules), although necessary differences in the crossover operator may also explain the results. In principle, JavaGenes should be able to evolve other graph-representable systems, such as transportation networks, metabolic pathways, and computer networks. However, large graphs evolve significantly slower than smaller graphs, presumably because the space-of-all-graphs explodes combinatorially with graph size. Since the representation strongly affects genetic algorithm performance, adding graphs to the evolutionary programmer's bag-of-tricks should be beneficial. Also, since graph evolution operates directly on the phenotype, the genotype-phenotype translation step, common in genetic algorithm work, is eliminated.

Globus, Al↗

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

High-Rate Ka-Band Modulator for the NISAR Mission

In order to meet ever-increasing data return requirements, more satellites are using the near-Earth Ka-band (25.5 – 27.0 GHz) to achieve higher downlink rates. The paper discusses the Universal Space Transponder - Ka-band Modulator (UST-KaM) developed at the NASA Jet Propulsion Laboratory for the NASA-ISRO SAR (NISAR) mission, which is capable of transmitting up to 1.74 Gbps with 7/8 LDPC encoding. The UST-KaM utilizes OQPSK with both baseband and RF filtering to contain the 1 Gsps transmission spectrum within the 1.5 GHz Ka-band, even with the use of an external, saturated amplifier. Due to the high data rates involved, several technical hurdles were overcome in both the digital and RF designs. The UST-KaM is a software defined radio with two digital circuit board assemblies: a low speed housekeeper board for commanding and telemetry, and a high-rate signal processing board known as the Signal Processing Module (SPM). The SPM receives data from the spacecraft via a SERDES interface at up to 2 Gbps, processes and encodes the data using a Xilinx Virtex-5 FPGA, and produces 1 Gsps OQPSK I and Q waveforms via synchronized, multiplexed DACs. The RF Electronics in the UST-KaM employ a heterodyne architecture in which the I/Q digital waveforms are filtered and then up-converted using a sub-harmonic IQ mixer. The LO of the converter, which is included in the exciter assembly, is at 13.125GHz, and the RF output is a 26.25GHz carrier which is modulated with the OQPSK waveforms. The output of the mixer is then filtered using low loss quartz thinfilm edge coupled Chebyshev filters and amplified through a series of low gain Ka-Band amplifiers. The exciter assembly also has a 2GHz, low-phase-noise, PLL synthesizer to supply the clock to the DACs for the high rate digital waveforms.

Spurgers, Carl↗

The Development of Si and SiGe Technologies for Microwave and Millimeter-Wave Integrated Circuits

Historically, microwave technology was developed by military and space agencies from around the world to satisfy their unique radar, communication, and science applications. Throughout this development phase, the sole goal was to improve the performance of the microwave circuits and components comprising the systems. For example, power amplifiers with output powers of several watts over broad bandwidths, low noise amplifiers with noise figures as low as 3 dB at 94 GHz, stable oscillators with low noise characteristics and high output power, and electronically steerable antennas were required. In addition, the reliability of the systems had to be increased because of the high monetary and human cost if a failure occurred. To achieve these goals, industry, academia and the government agencies supporting them chose to develop technologies with the greatest possibility of surpassing the state of the art performance. Thus, Si, which was already widely used for digital circuits but had material characteristics that were perceived to limit its high frequency performance, was bypassed for a progression of devices starting with GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and ending with InP Pseudomorphic High Electron Mobility Transistors (PHEMTs). For each new material or device structure, the electron mobility increased, and therefore, the high frequency characteristics of the device were improved. In addition, ultra small geometry lithographic processes were developed to reduce the gate length to 0.1 pm which further increases the cutoff frequency. The resulting devices had excellent performance through the millimeter-wave spectrum.

Ponchak, George E.↗

Building Reliable Printed Circuit Boards - the Lessons Learned

"Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues."

Sood, Bhanu↗

Flux trapping in NbTiN strips

We use scanning superconducting quantum interference device (SQUID) microscopy to image vortices in superconducting structures fabricated from NbTiN thin films. We repeatedly cool superconducting strips with different width in an applied magnetic field and image the individual vortices. From these images we determine the threshold field at which the first vortex enters a strip and the number and configuration of vortices beyond this threshold field. We model the behavior of the vortices with and without considering the effect of pinning using numerical methods to minimize the Gibbs free energy of vortices in the strips. Our measurements provide a first benchmark to investigate the flux trapping properties of NbTiN thin films directly relevant to NbTiN-based superconducting digital circuits.

Bai, Ruiheng [Cornell University] (ORCID:000000025↗

A Method to Probe the Interfaces in La2−xSrxCuO4-LaSrAlO4-La2−xSrxCuO4 Trilayer Junctions

C-axis trilayer cuprate Josephson junctions are essential for basic science and digital circuit applications of high-temperature superconductors. We present a method for probing the interface perfection in La2−xSrxCuO4 (LSCO)-LaSrAlO4 (LSAO)-La2−xSrxCuO4 trilayer junctions. A series of LSCO-LSAO superlattices with atomically smooth surfaces and sharp interfaces were grown by the atomic-layer-by-layer molecular beam epitaxy (ALL-MBE) technique. We have systematically varied the thickness of LSCO and LSAO layers with monolayer precision. By studying the mutual inductance and electrical transport in these superlattices, we detect the non-superconducting (“dead”) layers at the interfaces and quantify their thicknesses. Our results indicate that two optimally doped LSCO monolayers just above and below the one monolayer LSAO barrier are no longer superconducting, rendering the actual barrier thickness of five monolayers. Next, we have shown that introducing a protective highly-overdoped LSCO layer reduces the thickness of dead layers by one or two monolayers.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Frequency correction device uses digital circuitry

Signal acquisition and tracking system covering a wide range of frequencies uses a digital circuit to sample the frequency of an incoming signal and provide correction pulses to the voltage-controlled oscillator. The circuit can also sense the presence of a signal on any one of the input lines.

Schaefer, D.↗

A continued fraction generator for smooth pulse sequences

Digital circuit produces rational output pulse rate at fraction of continuous input pulse rate. Output pulses have average rate with least possible deviation from absolute correct time spacing. Circuit uses include frequency synthesizing, fraction generation, and approximation of irrational sequences.

Cohn, M.↗

Ferrite logic reliability study

Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)

Baer, J. A.↗

Microprogrammed digital filters for strapdown guidance application.

Discussion of an approach for implementing digital filters using microprogrammed control logic with read only memory (ROM) for strapdown guidance applications, and description of a second-order multiplexed system using multiprogrammed control instruction. The microprogramming technique for control using ROM is shown to enhance higher order digital filter realization. The high speed of digital circuits reduces propagation time and facilitates multiplexing. Programmed ROM's can be altered easily for different algorithms.

Kapadia, K.↗

Reduction of quantization error in measurement of frequency

Method reduces quantization errors using new digital circuit. Circuit provides very high resolution (10 to the minus 2nd power to 10 to the minus 3rd power Hz) without high-speed counters. It lends itself to microminaturization and is simple to construct. Unknown frequency is compared to standard frequency by means of zero-crossing coincidence-detecting circuit.

Nossen, E. J.↗