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At least 883 records · Page 49
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NASA NTRSDate not supplied

Benchmarking Computational Tools for Calling SNPs and Indels in Complex Microbial Populations

The NASA BioNutrients missions seek to understand the suitability of microorganisms for bioproduction during space flight. One topic of interest is the stability of microbial genomes during long-term ambient storage and subsequent rehydration and growth. To address these questions, samples from 8 species were flown to ISS for 5 years of desiccated storage at ambient temperature (Stasis Packs) and 2 species were packaged along with powdered media inside a bioreactor system to allow hydration and growth in microgravity (Production Packs). For both systems, Whole Genome Sequencing (WGS) of the DNA extracted from the returned samples and paired ground controls will be conducted to identify changes in genome stability due to time, storage conditions and growth in space. Across the technical replicates, ground controls, 10 timepoints, and multiple experimental conditions, ~300 samples have been selected for initial analysis with WGS sequencing to 100x coverage. A flexible and resource efficient mutation calling pipeline is needed to process this large dataset and allow for comparisons between species. Many bioinformatics tools for calling Indels and Single Nucleotide Variants (SNVs) are designed for use with pure isolates, where true variations from the reference genome are expected to dominate the reads aligning to the location of mutation. In contrast, DNA from the Stasis Pack (SP) samples was collected directly after recovery from desiccated storage and the Production Pack (PP) samples were collected after fermentation. In this context, reads with mutations are expected to be less frequent than reads that align with the reference genome, as each sample will include multiple lines of cells. Thus, BioNutrients samples are expected to be similar to samples from cancer cell or “pooled” sequencing approaches. In preparation for the analysis of the BioNutrients samples, we have tested three mutation calling tools (GATK for Microbes, BreSeq and DiscoSNP) designed for complex samples. A challenge of validating mutation identification pipelines is a lack of “Ground Truth” datasets, especially for complex samples. To compare these three tools, we sought to identify mutations in pre-existing WGS data collected from populations of Chlamydomonas reinhardtii that were exposed to UV mutagenesis and growth in LEO as part of the Space Algae-1 mission. Here we present a summary of these tools against the analysis originally conducted using the CRISP tool. Critical metrics are compared such as runtime, the number of SNPs, the number and size of Indels, and patterns of transversion and transitions identified by each tool are reported. By sharing these benchmarking results collected in support of the BioNutrients mission, we aim to guide others seeking to identify SNVs in similarly complex microbial samples.

Biology↗
NASA NTRS2024

Launch Complex 34, SWMU CC054 2023 DNAPL Source Zone Operations, Maintenance, and Monitoring, Site-Wide Long-Term Monitoring, and Hot Spot 6 Air Sparge System Annual Performance Monitoring and Phase Two Expansion Construction Completion Report Cape Canaveral Space Force Station, Florida

This Annual Performance Monitoring Report (PMR) for the Dense Non-Aqueous Phase Liquid (DNAPL) Source Zone (DSZ), Site-Wide Long-Term Monitoring (LTM), and Hot Spot 6 (HS 6) Air Sparge (AS) System presents the results of Year 14 operations and performance monitoring of the hydraulic containment (HC) Interim Measure (IM), details associated with construction and implementation of the HS 6 AS system expansion (Phase Two), and the results of operations and performance sampling of the HS 6 AS IM at Launch Complex 34 (LC34), located at Cape Canaveral Space Force Station (CCSFS), Florida. The timeframe for activities documented in this PMR extends from April 1, 2023 to March 31, 2024. LC34 has been designated Solid Waste Management Unit CC054 under the Kennedy Space Center (KSC) Resource Conservation and Recovery Act Corrective Action Program. The objective of the HC IM at LC34 is to contain the shallow and deep DSZ and surrounding dissolved-phase trichloroethene (TCE) high concentration plume via operation of a hydraulic containment system (HCS). The pre-IM design 300 micrograms per liter (μg/L) TCE groundwater contour was used to establish the deep zone capture area for deep recovery wells, and the shallow zone capture area was defined by the DSZ. The system began operating in 2010, and in 2015, the system was expanded to provide HC for areas within the 300 μg/L TCE groundwater isocontours of HS 3 and 4. In 2018 and 2019, an investigation was conducted to recharacterize the DSZ, which included investigating TCE mass in Layer 7. This data was subsequently used to optimize the pumping rates of the HCS and install additional recovery wells in Layer 7 to more adequately capture residual contaminant mass. The operational period for Year 14 of the HCS was from April 1, 2023 to March 31, 2024. Operational runtime for the system was 94 percent during Year 14, with downtime events attributed to planned maintenance, system repairs, and power outages. As of March 31, 2024, a total of 344,849,634 cumulative gallons of groundwater containing 94,656 pounds of chlorinated volatile organic compounds (CVOCs) have been removed by the HCS. During the reporting period covered under this report, the HCS recovered 31,176,393 gallons and approximately 6,319 pounds of CVOC mass. Total combined influent concentrations of TCE have decreased since startup from approximately 280,000 µg/L (January 2010) to 25,000 µg/L (March 2024). During the reporting period, all effluent concentrations from the HCS (aqueous and vapor) were below regulatory reporting limits, indicating the system continues to operate as intended. Performance monitoring was conducted in January 2024 within the DSZ to evaluate TCE contamination. Groundwater samples were collected via DPT at nine locations, consistent with previous events between 2017 and 2022. Full vertical profile sampling was completed at each DPT from 8 to 98 feet below land surface (bls), at 5-foot intervals. The DPT performance monitoring results are summarized in this PMR. The results revealed TCE remains at concentrations greater than 11,000 µg/L in the DSZ (1-percent solubility, indicative of DNAPL) at eight of the nine DPT locations and at depths ranging from 28 to 98 feet bls. An overall decreasing trend of TCE concentrations was observed in DPT samples during this reporting period, which is a reduction from the previous event (December 2022) and the peak event in December 2021, where TCE percentages appeared to increase in all depth zones because several recovery wells were turned off during the AS pilot study in the DSZ. The maximum TCE concentration in January 2024 was 1,600,000 µg/L in the 53 feet bls depth interval at DPT594 (previous maximum result in 2022 was 1,800,000 µg/L in the 48 feet bls depth interval at DPT599). This maximum concentration in the 53 feet bls depth interval is in the deep capture zone. During the January 2024 DPT event, the largest portion of TCE mass was observed in the 48 feet bls interval above/within Layer 4. This trend remains consistent with previous years and appears to indicate continued mass discharge from Layer 4 (fine-grained unit). In addition to DPT sampling, annual groundwater samples were collected from 11 deep monitoring wells in the DSZ area (Layers 7 and 8) in December 2023 to verify vertical and horizontal delineation. Three of the wells were also sampled biweekly to evaluate operations of recovery well RW21D (screened 86 to 106 feet bls), which was installed in January 2023. Of the Layer 7/8 monitoring sampled only annually, results were non-detect or less than groundwater cleanup target levels GCTLs in December 2023, with the exception of one well, IW45D2, which had a cis-1,2-dichloroethene (cDCE), detection greater than the GCTL. Of the three wells sampled biweekly during the operational period, the well located closest to Layer 7 recovery well RW21D (IW44D2, screened 105 to 115 feet bls) had concentrations of TCE, cDCE and vinyl chloride (VC) greater than GCTLs throughout the operational period, but displayed a decreasing trend since the peak concentrations in September 2023. The maximum TCE concentration during this operational period was 190,000 µg/L at IW44D2 in September 2023, but reduced to 700 µg/L in March 2024, indicating the HCS is still effectively removing mass from the source area. Expansion of the HCS and addition of new recovery wells is ongoing and will continue to be evaluated as the groundwater recovery scheme is optimized. Details of the expansion and optimization will be provided in a future PMR. The HS 6 AS IM was initiated in 2018 with 160 AS wells and expanded in 2019 with another 140 AS wells. An additional expansion of the HS 6 AS IM was completed during the reporting period covered under this report and details of the construction implementation and startup of the expansion are detailed in Section III of this report. The new expansion, referred to as Phase Two, was implemented between August 17, 2022 and August 28, 2023, and included the installation of 190 air sparge wells to treat an additional 11.2 acres. The original configuration (referred to as Phase One) operated until Phase Two came online, then all but 52 AS wells were turned off so the components could be moved and utilized in the Phase Two area. The 52 AS wells that remain on are in a barrier configuration preventing contaminated groundwater from impacting the treated area. The HS 6 AS system (both Phase One and Two) operated normally during the reporting period covered under this report. Semi-annual performance monitoring of the Phase One configuration was conducted in April and November 2023, consistent with previous years. For the Phase Two configuration, 21 new monitoring wells were installed and sampled quarterly, with a baseline event in July 2023, and quarterly events in November 2023 and February 2024 summarized in this report. Semi-annual monitoring results collected in April and October 2023 show concentrations of contaminants of concern (cDCE, trans-1,2-dichloroethene, and VC) have decreased to less than GCTLs in nearly all wells and not impacting the surface water drainage canal, indicating the HS 6 IM continues to meet objectives. The baseline and quarterly sampling for the Phase Two configuration indicate generally decreasing concentrations in wells within and around the perimeter of the treatment area. At least two more quarters of monitoring will be conducted and once those results are evaluated a reduced the sampling frequency may be considered. Overall, the tasks associated with Year 14 operation of the HC IM and operation of the HS 6 AS IM were performed in accordance with recommendations included in the previous 2022 LC34 (Year 13) PMR. Evaluation of results from the HC IM and HS 6 IM show that these systems are operating as designed and meeting performance objectives.

groundwater remediation↗
NASA NTRS2025

Robust Trajectory Optimization for NRHO Rendezvous Using SPICE Kernel Relative Motion

In this paper, robust optimization is performed on trajectory correction maneuvers during the lunar lander return phase of an Artemis mission, treating the trajectory from one hour after low lunar orbit departure to arrival in the vicinity of the lunar Gateway as a relative motion problem. To enable rapid stochastic optimization techniques requiring many candidate trajectories, SPICE kernel relative motion as implemented by the Quadratic Interpolated State Transition (QIST) system is used as the underlying dynamics propagation. The optimization is performed with a genetic optimizer using linear covariance (LinCov) software in a simplified operational context, taking into account the availability of navigation sensors with varying measurement models, ranges, and accuracies. No numerical integration is used, since the relative motion around Gateway is fully characterized with the a priori computation of the QIST coefficients. Maneuver placements are computed to optimize the minimum 3σ delta-v of the trajectory, the position dispersion at a target point, and a convex combination of these two metrics. An order of magnitude runtime improvement is provided over legacy methods with less than 10% error introduced. All QIST results are shown to be in-family with legacy methods. The tradespace for optimal delta-v design is found to range from 77.0 to 93.9 m/s, while the range of optimal dispersion is between 1.4 and 11.7 km.

Relative Motion↗
NASA NTRSDate not supplied

Assembly and Integration Status of a High Fidelity Ground Test Bed for the Water Processor Assembly

The Water Recovery System (WRS) is a critical component of life support aboard the International Space Station (ISS) and will play an essential role in future missions beyond Low Earth Orbit (LEO). Its primary functional units – the Urine Processor Assembly (UPA), Brine Processor Assembly (BPA), and Water Processor Assembly (WPA) – must be evaluated for extended operation, dormancy resilience, material obsolescence, and reliability under exploration-driven constraints. Ground testing is vital for developing these technologies and generating statistically relevant reliability assessments, which requires extended runtime under integrated, Flight-like conditions. Currently, no high-fidelity, fully integrated WPA ground test bed exists to support these objectives. To address this gap, NASA is developing a WPA test bed at Marshall Space Flight Center (MSFC) that combines downgraded ISS flight hardware with functionally flight-like components in a cost-effective configuration while maintaining priority hardware investigations. This paper describes the current status of hardware assembly and integration, outlines key challenges such as simulating microgravity effects and mitigating obsolescence, and presents future test objectives including software development, reliability assessments, dormancy studies, and exploration-oriented upgrades.

Mary-Elizabeth Davis↗
NASA NTRSDate not supplied

Assembly and Integration Status of a High Fidelity Ground Test Bed for the Water Processor Assembly

The Water Recovery System (WRS) is a critical component of life support aboard the International Space Station (ISS) and will play an essential role in future missions beyond Low Earth Orbit (LEO). Its primary functional units – the Urine Processor Assembly (UPA), Brine Processor Assembly (BPA), and Water Processor Assembly (WPA) – must be evaluated for extended operation, dormancy resilience, material obsolescence, and reliability under exploration-driven constraints. Ground testing is vital for developing these technologies and generating statistically relevant reliability assessments, which requires extended runtime under integrated, Flight-like conditions. Currently, no high-fidelity, fully integrated WPA ground test bed exists to support these objectives. To address this gap, NASA is developing a WPA test bed at Marshall Space Flight Center (MSFC) that combines downgraded ISS flight hardware with functionally flight-like components in a cost-effective configuration while maintaining priority hardware investigations. This paper describes the current status of hardware assembly and integration, outlines key challenges such as simulating microgravity effects and mitigating obsolescence, and presents future test objectives including software development, reliability assessments, dormancy studies, and exploration-oriented upgrades.

Water Processor Assembly↗
DOE OSTI2020

Network packet templating for GPU-initiated communication

Systems, apparatuses, and methods for performing network packet templating for graphics processing unit (GPU)-initiated communication are disclosed. A central processing unit (CPU) creates a network packet according to a template and populates a first subset of fields of the network packet with static data. Next, the CPU stores the network packet in a memory. A GPU initiates execution of a kernel and detects a network communication request within the kernel and prior to the kernel completing execution. Responsive to this determination, the GPU populates a second subset of fields of the network packet with runtime data. Then, the GPU generates a notification that the network packet is ready to be processed. A network interface controller (NIC) processes the network packet using data retrieved from the first subset of fields and from the second subset of fields responsive to detecting the notification.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Vertex Reordering for Real-world Graphs and Applications: An Empirical Evaluation

Vertex reordering is a way to improve locality in graph computations. Given an input (or ``natural'') order, reordering aims to compute an alternate permutation of the vertices that is aimed at maximizing a locality-based objective. Given decades of research on this topic, there are tens of graph reordering schemes, and there are also several linear arrangement ``gap'' measures for treatment as objectives. However, a comprehensive empirical analysis of the efficacy of the ordering schemes against the different gap measures, and against real-world applications is currently lacking. In this study, we present an extensive empirical evaluation of up to 11 ordering schemes, taken from different classes of approaches, on a set of 34 real-world graphs emerging from different application domains. Our study is presented in two parts: a) a thorough comparative evaluation of the different ordering schemes on their effectiveness to optimize different linear arrangement gap measures, relevant to preserving locality; and b) extensive evaluation of the impact of the ordering schemes on two real-world, parallel graph applications, namely, community detection and influence maximization. Our studies show a significant divergence among the ordering schemes (up to $40\times$ between the best and the poor) in their effectiveness to reduce the gap measures; and a wide ranging impact of the ordering schemes on various aspects including application runtime (up to $4\times$), memory and cache use, load balancing, and parallel work and efficiency. The comparative study also help reveal the nuances of a parallel environment (compared to serial) on the ordering schemes and their role in optimizing applications.

Barik, Reet↗
DOE OSTI2020

CQNN: a CGRA-based QNN Framework

We propose a novel Coarse-Grained Reconfigurable Architecture-based (CGRA) QNN acceleration framework, CQNN. CQNN has a large number of basic components for binary functions. By programming CQNN at runtime according to the target QNN models, these basic components are integrated efficiently to support QNN functions with any data-width and hyper-parameter requirements and CQNN is reconfigured to have the optimal architecture for the target models. The framework includes compiler, architecture design, simulator and RTL generator. Experimental results show CQNNs can complete the inference of AlexNet and VGG-16 within 0.13ms and 2.63ms.

Geng, Tong↗
DOE OSTI2020

Locality-Aware Scheduling for Scalable Heterogeneous Environments

Heterogeneous computing promise boost performance of scientific applications by allowing massively parallel execution of computational tasks. However, manually managing extremely heterogeneous, multi-device systems is complicated and may result in sub-optimal performance. Specifically, data management is an extremely challenging problem on multi-device systems. In this work, we introduce two locality-aware schedulers for the Minos Computing Library (MCL), an asynchronous, task-based programming model and runtime for extremely heterogeneous systems. The first scheduler implements a pure locality-aware algorithm to maximize data reuse, though it might incur in ”hot-spots” that limit system utilization. The second scheduler mitigates this drawback by dynamically targeting between locality-awareness and system utilization based on the current workload and available computing devices. Our results show that locality-awareness greatly benefit applications that exhibit data reuse, providing up to 6.9x and 7.9x over the original MCL scheduler and equivalent OpenCL implementations, respectively. Moreover, our schedulers introduce negligible overhead compared with the original MCL scheduler and achieve similar performance for applications that don’t benefit from data locality.

Architecture, co-design, Task-based programming mo↗
DOE OSTI2020

Towards Generic Parallel Programming in Computer Science Education with Kokkos

Parallel patterns, views, and spaces are promising abstractions to capture the programmer's intent as well as the contextual information that can be used by an underlying runtime to efficiently map software to parallel hardware. These abstractions can be valuable in cases where an algorithm must accommodate requirements of code and performance portability across hardware architectures and vendor programming models. Kokkos is a parallel programming model for host- and accelerator architectures that relies on these abstractions and targets these requirements. It consists of a pure C++ interface, a specification, and a programming library. The programming library exposes patterns and types and maps them to an underlying abstract machine model. The abstract machine model offers a generic view of parallel hardware. While Kokkos is gaining popularity in large-scale HPC applications at some DOE laboratories, we believe that the implemented concepts are of interest to a broader audience including academia as they may contribute to a generic, vendor, and architecture-independent education of parallel programming. In this work, we give an insight into the design considerations of this programming model and list important abstractions. Further, we document best practices obtained from giving virtual classes on Kokkos and give pointers to resources that the reader may consider valuable for a lecture on generic parallel programming for students with preexisting knowledge on this matter.

Ciesko, Jan↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
DOE OSTI2021

Toward Performance Portable Programming for Heterogeneous System-on-Chips: Case Study with Qualcomm Snapdragon SoC

Future heterogeneous Domain-Specific System-on-Chips (DSSoC) will be extraordinarily complex in terms of processors, memory hierarchies, and interconnection networks.To manage this complexity, architects, system software designers, and application developers need programming technologies that are flexible, accurate, efficient, and productive. These technologies will need to be as independent of any one specific architecture as is practical, because the sheer dimensionality and scale of the complexity will not allow porting and optimizing applications foreach given DSSoC. To address these issues, we are developing Cosmic Castle, a performance portable programming toolchain for streaming applications on heterogeneous architectures. The primary focus of Cosmic Castle is on enabling efficient and performant code generation through the smart compiler and intelligent runtime system. This paper presents the preliminary evaluation of our ongoing work toward Cosmic Castle. Specifically, we detail our code porting efforts and evaluate various benchmarks on the Qualcomm Snapdragon SoC using tools developed through Cosmic Castle.

Cabrera, Anthony↗
DOE OSTI2021

RMACXX: An Efficient High-Level C++ Interface over MPI-3 RMA

Parallel scientific applications can benefit from de- coupling communication and synchronization. One-sided pro- gramming abstractions, which separate communication from syn- chronization, have in fact served as a motivation for partitioned global address space (PGAS) models. However, the use of PGAS models in application codes in a manner that fully exploits the benefit of these programming models requires significant development effort. Meanwhile, a vast majority of scientific codes already use the Message Passing Interface (MPI) and need convenient features to support application-specific one-sided communication scenarios. MPI Remote Memory Access (RMA) can be employed for this purpose. MPI is a low-level API, however, and developing applications with MPI RMA requires programmers to be well versed in its nuances. We present RMACXX, a compact set of C++ bindings to MPI-3 RMA, to ease the use of MPI RMA. Unlike other PGAS models, which may have interoperability issues with MPI, RMACXX is written on top of MPI and uses the same runtime as MPI. The basic functionality of RMACXX adds only a relatively small number of extra instructions (about 20) to the critical communication path. Moreover, RMACXX provides an intuitive API for building a wide variety of scientific applications while enjoying performance matching handwritten MPI-3 RMA codes.

MPI-3 RMA, one-sided communication, PGAS, C++, exp↗
DOE OSTI2021

Memory object tagged memory monitoring method and system

Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

Roberts, David A.↗
DOE OSTI2022

Accelerating the Inference of the Exa.TrkX Pipeline

Recently, graph neural networks (GNNs) have been successfully used for a variety of particle reconstruction problems in high energy physics, including particle tracking. The Exa.TrkX pipeline based on GNNs demonstrated promising performance in reconstructing particle tracks in dense environments. It includes five discrete steps: data encoding, graph building, edge filtering, GNN, and track labeling. All steps were written in Python and run on both GPUs and CPUs. In this work, we accelerate the Python implementation of the pipeline through customized and commercial GPU-enabled software libraries, and develop a C++ implementation for inferencing the pipeline. The implementation features an improved, CUDA-enabled fixed-radius nearest neighbor search for graph building and a weakly connected component graph algorithm for track labeling. GNNs and other trained deep learning models are converted to ONNX and inferenced via the ONNX Runtime C++ API. The complete C++ implementation of the pipeline allows integration with existing tracking software. We report the memory usage and average event latency tracking performance of our implementation applied to the TrackML benchmark dataset.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Apptainer Without Setuid

Apptainer (formerly known as Singularity) since its beginning implemented many of its container features with the assistance of a setuid-root program. It still supports that mode, but as of version 1.1.0 it no longer uses setuid by default. This is feasible because it now can mount squash filesystems, mount ext2/3/4 filesystems, and use overlayfs using unprivileged user namespaces and FUSE. It also now enables unprivileged users to build containers, even without requiring system administrators to configure /etc/subuid and /etc/subgid unlike other "rootless" container systems. As a result, all the unprivileged functions can be used nested inside of another container, even if the container runtime prevents any elevated privileges.

Dykstra, Dave↗
DOE OSTI2022

Masked fault detection for reliable low voltage cache operation

Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

Ganapathy, Shrikanth↗