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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 865 records · Page 48
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗
DOE OSTI2018

Providing a Graphical Tool for Modeling Reactor Cores

Complex, coupled physical systems that occur in various domain sciences present several serious challenges in implementing an efficient and seamless simulation workflow. These challenges impact the productivity of scientific research and the overall time it takes to verify simulation results. To overcome these computational modeling barriers, specifically in nuclear reactor analysis, one must rely on flexible and scalable tools that simplify modeling complexity.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units

A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

97 MATHEMATICS AND COMPUTING↗