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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 865 records · Page 48
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Observation of radiation induced changes in stress and electrical properties in MOS devices

Strain measurements using X-ray diffraction were performed on irradiated commercial and radiation-hardened metal gate CMOS devices in addition to polysilicon gate NMOS devices. I-V curves were taken and V(ot) and V(it) were separated using the subthreshold slope method for all devices. A correlation has been shown to exist between physical strain relaxation and the electrical properties as a function of radiation dose and recovery. Data shown suggest that the physical response (strain relaxation) in the silicon at the oxide interface is a measure of the type of damage induced and the recovery mechanism. Postradiation measurements of Delta V(it) and Delta V(ot) taken immediately after irradiation support the conclusions of V. Zekeriya and T.-P. Ma (1983) and K. Kasama et al. (1986, 1987); compressive stress at the silicon/SiO2 interface does reduce radiation damage in the device.

Shaw, D. C.↗
NASA NTRS1992

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Fossum, Eric R.↗
NASA NTRS1992

Unfulfilled needs in IR astronomy focal-plane readout electronics

The NOAO's 8-m IR optimized telescope for Mauna Kea and NASA's SIRTF show that from 1 to 200 microns there are a number of unfulfilled needs in readout electronics. These include: extremely low readnoise, less than 10 electrons, stable operation at temperatures as low as 2 K, high well capacity, greater than 1 e 7 electrons, and integration times from 30 msec to over 100 sec. Sensors for adaptive optics systems are required with readnoise less than 10 electrons and response times of 30 msec. They should be highly efficient from 1 to 2.5 microns, but may have small formats. Ground-based imagers at these wavelengths need comparable readnoise but longer integration times, and the largest possible formats are essential. To achieve these goals improved cryogenic MOSFETS are essential and complete cryogenic CMOS circuits are highly desirable. Experimental cryoptimized MFETS promise to exceed the above noise requirements at 77 K and approach the needs at 2 K.

Low, Frank J.↗
NASA NTRS1992

Low power, highly linear output buffer

A class AB CMOS output buffer has been designed for use on an IR focal plane array. Given the requirements for power dissipation and load capacitance a class A output, such as a source follower, would be unsuitable. The approach taken uses a class AB amplifier configured as a charge integrator. Thus it converts a charge packet in the focal plane multiplexer to a voltage which is then the output of the focal plane. With a quiescent current of 18 micro-a and a load capacitance of 100 pf, the amplifier has an open loop unity gain bandwidth of 900 khz. Integral nonlinearity is better than .03 percent over 5.5 volts when run with VDD-VSS = 6v.

Foley, D.↗
NASA NTRS1993

A low-power battery ampere-hour meter

A digital device has been developed to meter the current drain of a battery in ampere hours. The device consists of a voltage controlled oscillator (VCO), a frequency divider, an accumulator, and a liquid crystal display. A voltage proportional to load current is converted into a clock signal whose pulse rate is scaled by the frequency divider to the desired engineering units. Final output pulses are counted and displayed. The use of MOSFET and CMOS integrated circuits allows continuous battery-powered operation over a 3-month time period to an accuracy of +/- 2 percent. The instrument will find application where accurate monitoring of battery charge/discharge status is required over long time intervals.

Tripp, John S.↗
NASA NTRS1983

Low background IR detector and detector array evaluations

A technology program has been underway at Ames since 1978 to develop and evaluate detectors and integrated detector arrays for low-background astronomical applications. The approach is to evaluate existing (less than 24 micron) array technology under low-background conditions, with the aim of adapting and optimizing existing devices. For longer wavelengths, where the technology is much less mature, development is sponsored and devices are evaluated, in both discrete and array formats, for eventual applications. The status of this program has been reported previously. We rely on industrial and university sources for the detectors. Typically, after a brief functionality check in the supplier's laboratory, we work with the device at Ames to characterize its low-background performance. In the case of promising arrays or detectors, we conduct ground-based telescope testing to face the problems associated with real applications. A list of devices tested at Ames is given. In the array category, accumulation-mode charge-injection-devices (AMCIDs) appear repeatedly; this reflects our recent experience with the 2 x 64 and 16 x 16 arrays. Results from the 1 x 16 CID and InSb CCD have been reported. The status of our tests of the discrete Ge:x detectors from Lawrence Berkeley Laboratory are described below. Tests of a 1 x 2 switched sample photoconductor array are just beginning. A 32-channel CMOS multiplexer has been tested at 10 K. Low-temperature silicon MOSFETs and germanium JFETs have also been tested, primarily at Ball Aerospace. This paper describes results to date on three elements of this program: AMCID array, discrete Ge:Ga detectors, and Ge JFET preamplifiers.

Goebel, J. H.↗
NASA NTRS1994

Making A D-Latch Sensitive To Alpha Particles

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Buehler, Martin G.↗
NASA NTRS1990

Self arbitrated VLSI asynchronous sequential circuits

A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

Whitaker, S.↗
NASA NTRS1990

PLA realizations for VLSI state machines

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Gopalakrishnan, S.↗
NASA NTRS1990

ACE: Automatic Centroid Extractor for real time target tracking

A high performance video image processor has been implemented which is capable of grouping contiguous pixels from a raster scan image into groups and then calculating centroid information for each object in a frame. The algorithm employed to group pixels is very efficient and is guaranteed to work properly for all convex shapes as well as most concave shapes. Processing speeds are adequate for real time processing of video images having a pixel rate of up to 20 million pixels per second. Pixels may be up to 8 bits wide. The processor is designed to interface directly to a transputer serial link communications channel with no additional hardware. The full custom VLSI processor was implemented in a 1.6 mu m CMOS process and measures 7200 mu m on a side.

Cameron, K.↗
NASA NTRS1990

High performance pipelined multiplier with fast carry-save adder

A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

Wu, Angus↗
NASA NTRS1993

RighTime: A real time clock correcting program for MS-DOS-based computer systems

A computer program is described which effectively eliminates the misgivings of the DOS system clock in PC/AT-class computers. RighTime is a small, sophisticated memory-resident program that automatically corrects both the DOS system clock and the hardware 'CMOS' real time clock (RTC) in real time. RighTime learns what corrections are required without operator interaction beyond the occasional accurate time set. Both warm (power on) and cool (power off) errors are corrected, usually yielding better than one part per million accuracy in the typical desktop computer with no additional hardware, and RighTime increases the system clock resolution from approximately 0.0549 second to 0.01 second. Program tools are also available which allow visualization of RighTime's actions, verification of its performance, display of its history log, and which provide data for graphing of the system clock behavior. The program has found application in a wide variety of industries, including astronomy, satellite tracking, communications, broadcasting, transportation, public utilities, manufacturing, medicine, and the military.

Becker, G. Thomas↗
NASA NTRS1991

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Source record↗
NASA NTRS1991

Automated ILA design for synchronous sequential circuits

An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.

Liu, M. N.↗
NASA NTRS1991

Training product unit neural networks with genetic algorithms

The training of product neural networks using genetic algorithms is discussed. Two unusual neural network techniques are combined; product units are employed instead of the traditional summing units and genetic algorithms train the network rather than backpropagation. As an example, a neural netork is trained to calculate the optimum width of transistors in a CMOS switch. It is shown how local minima affect the performance of a genetic algorithm, and one method of overcoming this is presented.

Janson, D. J.↗
NASA NTRS1991

Improved self arbitrated VLSI asynchronous circuits

This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.

Winterrowd, P.↗
NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗
NASA NTRS1993

Rad-hard computer elements for space applications

Space Hardened CMOS computer elements emulating a commercial microcontroller and microprocessor family have been designed, fabricated, qualified, and delivered for a variety of space programs including NASA's multiple launch International Solar-Terrestrial Physics (ISTP) program, Mars Observer, and government and commercial communication satellites. Design techniques and radiation performance of the 1.25 micron feature size products are described.

Krishnan, G. S.↗