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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 829 records · Page 46
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment

This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.

Riceputi, Elisa↗
DOE OSTI2020

Scalable quantum processor noise characterization

Measurement fidelity matrices (MFMs) (also called error kernels) are a natural way to characterize state preparation and measurement errors in near-term quantum hardware. They can be employed in post processing to mitigate errors and substantially increase the effective accuracy of quantum hardware. However, the feasibility of using MFMs is currently limited as the experimental cost of determining the MFM for a device grows exponentially with the number of qubits. In this work we present a scalable way to construct approximate MFMs for many-qubit devices based on cumulant expansions. Our method can also be used to characterize various types of correlation error.

Hamilton, Kathleen↗
DOE OSTI2023

Physical vapor deposition simulator by graphical processor unit ray casting

This paper presents fast, accurate software for modeling physical vapor deposition systems over irregular surfaces. The model is implemented using graphics processing unit (GPU) ray casting. Applied models are viewed as a cross section of the area of interest. Given evaporation rate, time, and angular profiles in a vacuum system, an iterative time-step approach for calculating deposition profiles is calculated in the GPU architecture following a ballistic modeling approach. Thin-film technologies for the electronics industry will require evaporations on complex surfaces. Depending on the nature of the surface, a uniform thin film across the topology is wanted for various device parameters. The ray casting method is tested against various profiles. The code is freely distributed on GitHub (see https://github.com/adam-r-thomas/PVDS).

Engineering↗
DOE OSTI2023

TISCC: A Surface Code Compiler and Resource Estimator for Trapped-Ion Processors

We introduce the Trapped-Ion Surface Code Compiler (TISCC), a software tool that generates circuits for a universal set of surface code patch operations in terms of a native trapped-ion gate set. To accomplish this, TISCC manages an internal representation of a trapped-ion system where a repeating pattern of trapping zones and junctions is arranged in an arbitrarily large rectangular grid. Surface code operations are compiled by instantiating surface code patches on the grid and using methods to generate transversal operations over data qubits, rounds of error correction over stabilizer plaquettes, and/or lattice surgery operations between neighboring patches. Beyond the implementation of a basic surface code instruction set, TISCC contains corner movement functionality and a patch translation that is implemented using ion movement alone. Except in the latter case, all TISCC functionality is extensible to alternative grid-like hardware architectures. TISCC output has been verified using the Oak Ridge Quasi-Clifford Simulator (ORQCS).

LeBlond, Tyler↗
DOE OSTI2021

Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors

Hardware platforms in high performance computing are constantly getting more complex to handle even when considering multicore CPUs alone. Numerous features and configuration options in the hardware and the software environment that are relevant for performance are not even known to most application users or developers. Microbenchmarks, i.e., simple codes that fathom a particular aspect of the hardware, can help to shed light on such issues, but only if they are well understood and if the results can be reconciled with known facts or performance models. The insight gained from microbenchmarks may then be applied to real applications for performance analysis or optimization. In this paper we investigate two modern Intel x86 server CPU architectures in depth: Broadwell EP and Cascade Lake SP. We highlight relevant hardware configuration settings that can have a decisive impact on code performance and show how to properly measure on-chip and off-chip data transfer bandwidths. The new victim L3 cache of Cascade Lake and its advanced replacement policy receive due attention. Finally we use DGEMM, sparse matrix-vector multiplication, and the HPCG benchmark to make a connection to relevant application scenarios.

97 MATHEMATICS AND COMPUTING↗