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At least 811 records · Page 45

Maximum Switching Throughput Density Estimator

SAND2024-11125O The Maximum Switching Throughput Density Estimator software performs a simple analysis that estimates the maximum logic switching throughput density that’s achieved in various CMOS technology nodes on the International Roadmap for Devices and Systems. This software utilizes simple device models and optimization techniques, performing a simple sweep over a range of possible logic supply voltages, and analytically calculating the maximum switching frequency for the given logic voltage that meets the power density constraint. It does this by using simple models of power dissipation in conventional and fully adiabatic switching. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Frank, Michael↗

Evaluation of the first version of the new RFPI system dedicated to PIP-II project accelerator

The Low-Level Radio Frequency (LLRF) control system is one of the most critical superconducting linac infrastructures responsible for the parameters of the beam acceleration. The LLRF system mainly focuses on the electromagnetic field parameters inside the cavity. While it incorporates fast feedback algorithms to optimize energy transfer to the passing particle beam it does not follow other cryomodule or cavity parameter changes. The Radio Frequency Protection Interlock (RFPI) system closely monitors various factors (like cryomodule vacuum, beamline vacuum, field emission probe current level, temperature, RF signal leakage, etc). Its simple but reliable logic has to provide an instant decision about the LLRF system or high-power amplifier output signal blocking in case of safety region excitation. This contribution presents a new version of the RFPI system which logic is implemented in the FPGA chip. The initial work on the prototype of the new system design resulted in the PoC (Proof of Concept) device. The PoC offers the possibility of various protection logic configurations, input signals parameters evaluation, and modularity aspects verification. The structure and test results from the device evaluation are summarized and discussed in this contribution.

43 PARTICLE ACCELERATORS↗

Graph Theory and IC Component Design Analysis

Graph analysis in large integrated circuit (IC) designs is an essential tool for verifying design logic and timing via dynamic timing analysis (DTA). IC designs resemble graphs with each logic gate as a vertex and the conductive connections between gates as edges. Using DTA digital statistical correlations, graph condensation, and graph partitioning, it is possible to identify high-entropy component centers and paths within an IC design. Identification of high-entropy component centers (HECC) enables focused DTA, effectively lowering the computational complexity of DTA on large integrated circuit graphs. In this paper, a devised methodology termed IC layout subgraph component center identification (CCI) is used to identify described. CCI lowers DTA computationally complexity by condensing IC graphs into reduced subgraphs in which dominant logic functions are verified.

42 ENGINEERING↗

Parsimonious Inference Information-Theoretic Foundations for a Complete Theory of Machine Learning (CIS-LDRD Project 218313 Final Technical Report)

This work examines how we may cast machine learning within a complete Bayesian framework to quantify and suppress explanatory complexity from first principles. Our investigation into both the philosophy and mathematics of rational belief leads us to emphasize the critical role of Bayesian inference in learning well-justified predictions within a rigorous and complete extended logic. The Bayesian framework allows us to coherently account for evidence in the learned plausibility of potential explanations. As an extended logic, the Bayesian paradigm regards probability as a notion of degrees of truth. In order to satisfy critical properties of probability as a coherent measure, as well as maintain consistency with binary propositional logic, we arrive at Bayes' Theorem as the only justifiable mechanism to update our beliefs to account for empiracle evidence. Yet, in the machine learning paradigm, where explanations are unconstrained algorithmic abstractions, we arrive at a critical challenge: Bayesian inference requires prior belief. Conventional approaches fail to yield a consistent framework in which we could compare prior plausibility among the infinities of potential choices in learning architectures. The difficulty of articulating well-justified prior belief over abstract models is the provinence of memorization in traditional machine learning training practices. This becomes exceptionally problematic in the context of limited datasets, when we wish to learn justifiable predictions from only a small amount of data.

97 MATHEMATICS AND COMPUTING↗

Model of Inverter-Based Resources

Blackbox modelling for SC analysis is a possible solution. Accuracy can be acceptable even without having vendor control diagrams. Is an NDA required to share a vendor Blackbox model for SC analysis? Differences in VRT detection and injection logics. Angle rotation is not addressed in control logics of most vendors. Current limitation logic during unbalanced faults is not clear. Model IBR as a current source with shunt to improve convergence

IBRs, Model of IBRs, Short Circuit Analysis, Class↗

Integrate Latimer Controls' Solution into RTAC (CRADA Final Report, CRD-23-24672)

Latimer Controls, Inc. was awarded two vouchers under the Department of Energy's American-Made Solar Prize Round 6 to conduct collaborative research at a national laboratory. The National Renewable Energy Laboratory (NREL) was selected as a partner to assist Latimer Controls in the performance evaluation of its photovoltaic (PV) control software. This collaboration focuses on developing a hardware-in-the-loop (HIL) testbed at NREL, which will be used to test and validate the Latimer PV control technology in a realistic yet de-risked environment. Both Latimer and NREL teams will work together to analyze the collected test data, derive insights, and disseminate the scientific findings. Recent studies underscore the potential of solar energy as a zero-marginal-cost and zero-emission flexibility resource within the bulk power system, particularly when integrated with advanced control systems. To enhance the performance of such systems, Latimer Controls has developed leading-edge technologies, including machine learning (ML) algorithms and hierarchical inverter set-point allocation methods. These innovations are designed to estimate the operational headroom of large PV plants for grid integration and control. However, comprehensive validation under real-world conditions remains necessary. To address this gap, the concurrent CRADA project proposes the real-world application and validation of the Latimer Control solution within a HIL environment. Initially, the Latimer algorithm was developed and tested within MATLAB Simulink, a platform suitable for research-level simulations and iterative development. However, transitioning this technology to a real solar site as an industry-ready solution necessitates implementation in a format compatible with widely used solar power plant controllers. In this additional CRADA work, the MATLAB Simulink-based logic will be translated into Structured Text, a programming language compliant with IEC 61131 standards, which is commonly used for custom logic implementations in industry-leading programmable logic controllers (PLCs), such as the Schweitzer SEL real-time automation controller (RTAC). This transition will facilitate the deployment of the Latimer Control solution in real-world solar power plants, thereby advancing the technology towards commercialization.

14 SOLAR ENERGY↗

Terra-Populus v0.1: A Python Library for LandScan High-Definition Population Analysis and Modeling

The terra-populus library is designed for use by the LandScan HD technical team, offering a streamlined set of tools for generating and updating LandScan HD datasets from foundational building-level data, referred to as 'molecules,' provided by the building-level attribution team. This document serves as the primary technical documentation for terra-populus. Version 0.1 of the library includes the core modeling components necessary for LandScan HD production. It enables the generation of the LandScan HD Baseline dataset as well as corresponding confidence measures for the occupancy rates used. Parameters have been included for incorporating damaged building indicators and changes in population, to faciliate the creation of rapid updates for LandScan HD. Future iterations of terra-populus will introduce tools for creating a confidence index, and quantifying and propagating uncertainty, facilitating the creation of probabilistic LandScan HD outputs. This report provides an overview of the tools available in the library and the corresponding code implementations. One of the key advancements implemented in terra-populus is a redefinition of the atomic modeling unit for LandScan HD. Traditionally, the LandScan HD vector analytical framework has generated population estimates at the building sub-component (molecule) level. However, terra-populus adopts a building-level modeling approach. This shift is an operational decision aimed at aligning LandScan HD outputs with confidence measures, which are computed and validated at the building level (confidence measures are not included in this version of terra-populus, aside from those associated with the occupancy rates). Additional advancements to the LandScan HD modeling, as implemented by terra-populus, include a minimum population value parameter and an auto assignment of building floor counts. The population minimum value was implemented to prevent buildings and subsequent LandScan HD pixels that contained small values that may not rasterize in production. An 'auto' value has been included as a method for dealing with buildings lacking floor count information, where it is the average floor count of all other buildings with a residential building use type tag. The logic behind this is to remain consistent with the current logic employed for dealing with building use type null instances, where a null use type is defaulted to residential since it is the most common building type. The auto logic is intended to apply the most common building floor count of the most common type of buildings. The tools provided in terra-populus represent a significant step forward in improving the efficiency, reproducibility, and transparency of the LandScan HD modeling process. As the library evolves, it will continue to serve as a foundational resource for high-resolution population modeling.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

Digital Grid Twin–Direct Communication Scheme Test Bed for Assessing Relay-to-Relay Radio Antenna and Optical Fiber Performance and Misoperations

This study introduces a novel “Digital Grid Twin–Direct Communication Scheme” test bed. This advanced platform evaluates point-to-point communication between transmitter and receiver relays with optical fiber and radio omnidirectional antenna systems, implemented at the Advanced Protection lab in the Grid Research Innovation and Development Center at Oak Ridge National Laboratory. The increased diversity of energy sources has led to more protective relay misoperations. In North America, microgrid protection schemes now use point-to-point communication along distribution lines between relays to implement advanced logic in nonradial grids that include both high- and low-inertia generators. This trend challenges utilities to minimize misoperations while ensuring rapid fault clearance and accurate selectivity coordination between primary and backup relays. This study assesses relay-to-relay communication schemes by introducing an advanced testing platform based on a digital grid twin protection test bed using a synchronized time source system. The platform evaluates the communication system using radio antennas or optical fiber links by integrating protective relays that operate breakers within the digital twin and record relay events and communication signals. In the experiments, transmitter and receiver relays were configured with inverse time overcurrent and breaker trip detection logic to assess the total time of the communication protection schemes based on the sum of the relay protection element operating time, radio latency, propagation delay, baud rate delay, and relay processing time. These delays were derived from recorded relay events and communication signals from the interface of a real-time simulator set as a digital grid twin. The test bed successfully simulated various electrical faults along a distribution line while ensuring effective and reliable point-to-point communication between transmitter and receiver relays. The radio antenna communication system exhibited latency because of the radio. This latency depends on the baud rate setting and type of radio application; in general, the higher the baud rate, the lower the radio latency. The measured radio latency (for Mirrored Bits with an encryption card at 9,600 bps) was about 9–10 ms. Additionally, calculated propagation delay per mile for radio antennas and optical fiber was 5.36 µs/mi and 8.04 µs/mi, respectively. Optical fiber communication did not demonstrate radio latency. Instead, the protection element operating time depends mainly on the protection logic function set in the relay, and the relay processing time depends on the processing rate of the relay in samples per power system cycle.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Investigating the Vulnerabilities of the Direct Transfer Trip Scheme for Network Protector Units in the Secondary Networks of Electric Power Distribution Grids

Network protector units (NPUs) are crucial parts of the protection of secondary networks to effectively isolate faults occurring on the primary feeders. When a fault occurs on the primary feeder, there is a path of the fault current going through the service transformers that causes a negative flow of current on the NPU connected to the faulted feeder. Conventionally, NPUs rely on the direction of current with respect to the voltage to detect faults and make a correct trip decision. However, the conventional NPU logic does not allow the reverse power flow caused by distributed energy resources installed on secondary networks. The communication-assisted direct transfer trip logic for NPUs can be used to address this challenge. However, the communication-assisted scheme is exposed to some vulnerabilities arising from the disruption or corruption of the communicated data that can endanger the reliable operation of NPUs. This paper evaluates the impact of the malfunction of the communication system on the operation of communication-assisted NPU logic. To this end, the impact of packet modification and denial-of-service cyberattacks on the communication-assisted scheme are evaluated. The evaluation was performed using a hardware-in-the-loop (HIL) co-simulation testbed that includes both real-time power system and communication network digital simulators. This paper evaluates the impact of the cyberattacks for different fault scenarios and provides a list of recommendations to improve the reliability of communication-assisted NPU protection.

direct transfer trip↗

Ground computer test trap

Test trap consists of logic nest of five printed circuit boards, plus power supply within the unit. Device monitors more than one logic area simultaneously, gives visual display of detected error, operates at computer speed, maintains readily available logic description of cards used, and is compatible with existing computer circuitry.

Fondrie, D. G.↗

Simulation of Mariner Mars 1971 spacecraft

Preparation for the Mariner Mars 1971 mission is reported, including an extensive training program for operations personnel during which the primary source of spacecraft data was a computer program simulating the spacecraft. The objectives of a simulation model for training purposes differed from objectives appropriate to a design or analysis model. Model subsystems were designed to provide realistic telemetry data reflecting changes due both to commands and environmental parameters affecting the spacecraft at various times during the mission. The spacecraft is modeled along two separate functional lines. Boolean operations are concentrated in the spacecraft logic model, which determines the spacecraft state or mode, while mathematical operations or algorithms are executed in computational subsystem models. Although logic parameters are interrogated as a part of each computational pass, actual logic model processing occurs only when a change-of-state input is generated by the operations organization. The program design, some of the special characteristics of each of the modeled subsystems, and how the model was used in support of mission operations training are presented.

Ausman, N. E., Jr.↗

Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.

Feller, A.↗

Design of automata theory of cubical complexes with applications to diagnosis and algorithmic description

The following problems are considered: (1) methods for development of logic design together with algorithms, so that it is possible to compute a test for any failure in the logic design, if such a test exists, and developing algorithms and heuristics for the purpose of minimizing the computation for tests; and (2) a method of design of logic for ultra LSI (large scale integration). It was discovered that the so-called quantum calculus can be extended to render it possible: (1) to describe the functional behavior of a mechanism component by component, and (2) to compute tests for failures, in the mechanism, using the diagnosis algorithm. The development of an algorithm for the multioutput two-level minimization problem is presented and the program MIN 360 was written for this algorithm. The program has options of mode (exact minimum or various approximations), cost function, cost bound, etc., providing flexibility.

Roth, J. P.↗

Feasibility investigation of a cellularly organized data processor

The application of cellular arrays to NASA missions was studied. Cellular arrays are iterative logical and memory structures which can be programmed to accomplish a wide variety of logical tasks. Used in long-duration space missions, spare cellular arrays can be remotely programmed to replace faulty logical subsystems as the need arises.

Minnick, R. C.↗

A new approach to telemetry data processing

An approach for a preprocessing system for telemetry data processing was developed. The philosophy of the approach is the development of a preprocessing system to interface with the main processor and relieve it of the burden of stripping information from a telemetry data stream. To accomplish this task, a telemetry preprocessing language was developed. Also, a hardware device for implementing the operation of this language was designed using a cellular logic module concept. In the development of the hardware device and the cellular logic module, a distributed form of control was implemented. This is accomplished by a technique of one-to-one intermodule communications and a set of privileged communication operations. By transferring this control state from module to module, the control function is dispersed through the system. A compiler for translating the preprocessing language statements into an operations table for the hardware device was also developed. Finally, to complete the system design and verify it, a simulator for the collular logic module was written using the APL/360 system.

Broglio, C. J.↗

Management of analytical redundancy in digital flight control systems for aircraft

This paper presents a design method for optimal redundancy management for nonlinear systems with application to highly maneuvering aircraft. The approach taken is based on selecting the failure states to be covered by the system design and constructing a cost function that represents the cost of making an incorrect decision. The decision logic which minimizes the cost requires a bank of extended Kalman filters running in parallel. This produces a severe computational requirement. To reduce this requirement, a suboptimal logic is developed based on using a nonlinear single-stage prediction algorithm in the filters with filter gains and decision logic selected using steady-state results obtained from a linearization of the vehicle and sensor dynamics. The design process is then applied to designing a redundancy management system for the F8-C aircraft. Results indicate that the system is superior in failure detection to a system using the same structure but using a linear single-stage prediction algorithm in the filters.

Montgomery, R. C.↗

Digital transmitter for data bus communications system

An improved digital transmitter for transmitting serial pulse code modulation (pcm) data at high bit rates over a transmission line is disclosed. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line.

Proch, G. E.↗

Banning standard cell engineering notebook

A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The information is presented in a form useful for systems designs, logic design, and the preparation of inputs to both sets of Design Automation programs for array design and analysis. A data sheet is provided for each cell and gives the cell name, the cell number, its logic symbol, Boolean equation, truth table, circuit schematic circuit composite, input-output capacitances, and revision date. The circuit type file, also given for each cell, together with the logic drawing contained on the data sheet provides all the information required to prepare input data files for the Design Automation Systems. A detailed description of the electrical design procedure is included.

Source record↗