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This paper summarizes and reports a radiation hardened Spacecraft Integrated Circuit Technology to be flown on board the Cassini spacecraft in 1997 A.D. The Multichip Module has been designed to have an operating life of fifeteen (15) years with appropriate derating guidelines for high reliability.
Hybrid pixel array detectors (PADs) have expanded the fidelity, frame rate and dynamic range for diffractive imaging in electron microscopes. With their high detective quantum efficiencies (DQE), the noise performance limited is by counting statistics. Consequently, improving the precision and quality of high-speed images requires increasing the linear dynamic range and the maximum usable beam current. Here we describe a new prototype hybrid PAD, our next-generation electron microscope pixel array detector (NG-EMPAD) that expands both the framing speed and dynamic range of our earlier EMPAD design. Like the EMPAD, electrons are detected directly in a 500 μm thick silicon sensor bonded pixel-by-pixel to a custom signal processing integrated circuit (IC). Each pixel in the IC integrates charge carriers produced by the high-energy incident electrons. Here, in-pixel circuitry uses a combination of techniques to extend the dynamic range, including adaptive gain switching and the quantitative excess charge dumping similar to the EMPAD. In-pixel buffering of signals during readout allows acquiring a new image while reading out the previously collected image, yielding an image collection duty cycle of nearly 100%.
The Compact Muon Solenoid collaboration is designing a new high-granularity endcap calorimeter, HGCAL, to be installed later this decade. As part of this development work, a prototype system was built, with an electromagnetic section consisting of 14 double-sided structures, providing 28 sampling layers. Each sampling layer has an hexagonal module, where a multipad large-area silicon sensor is glued between an electronics circuit board and a metal baseplate. The sensor pads of approximately 1.1 cm$^{2}$ are wire-bonded to the circuit board and are readout by custom integrated circuits. The prototype was extensively tested with beams at CERN's Super Proton Synchrotron in 2018. Based on the data collected with beams of positrons, with energies ranging from 20 to 300 GeV, measurements of the energy resolution and linearity, the position and angular resolutions, and the shower shapes are presented and compared to a detailed Geant4 simulation.
Design and performance of logic circuit chip for computerized design of MOS integrated circuit arrays
Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.
Data displayed on television image of experiment. Video images of experiment sent with digital data on experiment to remote station. Digital data raw and unformatted or in form of characters. For minimal power consumption, interface circuit built of CMOS and HMOS integrated-circuit chips. Buffer/decoder circuit enables experiment computer to communicate with board without excessive loading of computer bus by board. Memory multiplexer/memory array implements buffer-swapping scheme as one buffer is read, other filled with new data.
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.
The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.
Metal interconnection pattern deposited on integrated circuit or solar cell economically by thermal decomposition of metallo-organic compound. In proposed process beam from laser or quartz lamp swept over substrate in required metalization pattern; wherever beam impinges on substrate, radiant heat decomposes compound, depositing metal. Process requires less costly equipment and less time than conventional metalization. Process readily adaptable to very-large-scale integrated (VLSI) circuits.
Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.
This viewgraph presentation surveys the fastest Monolithic Millimeter-wave Integrated Circuit (MMIC) amplifiers to date; summarize previous solid state power amp results to date; reviews examples of MMICs, reviews Power vs. Gate periphery and frequency; Summarizes previous LNA results to date; reviews Noise figure results and trends toward higher frequency
Highly flexible, electrically conductive freestanding graphene membranes hold great promise for vibration-based applications. This study focuses on their integration into mainstream semiconductor manufacturing methods. We designed a two-mask lithography process that creates an array of freestanding graphene-based variable capacitors on 100 mm silicon wafers. The first mask forms long trenches terminated by square wells featuring cone-shaped tips at their centers. The second mask fabricates metal traces from each tip to its contact pad along the trench and a second contact pad opposite the square well. A graphene membrane is then suspended over the square well to form a variable capacitor. The same capacitor structures were also built on 5 mm by 5 mm bare dies containing an integrated circuit underneath. We used atomic force microscopy, optical microscopy, and capacitance measurements in time to characterize the samples.
The purpose of this project is to characterize and correlate Electrostatic Discharge (ESD) sensitivity levels of an Integrated Circuit (IC) package using Transmission Line Pulse (TLP) and Human Body Model (HBM) methods. This characterization will be used as a baseline ESD sensitivity level to demonstrate improvement to the ESD sensitivity of the IC package through the use of EPI-FLO(Trade Mark) Polymer Voltage Suppression (PVS) protection devices developed and manufactured by Electronic Polymers, Inc. (EPI).
The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.
The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.
This paper describes a set of power amplifier (PA) modules containing InP High Electron Mobility Transistor (HEMT) Monolithic Millimeter-wave Integrated Circuit (MMIC) chips. The chips were designed and optimized for local oscillator sources in the 90-130 GHz band for the Atacama Large Millimeter Array telescope. The modules feature 20-45 mW of output power, to date the highest power from solid state HEMT MMIC modules above 110 GHz.
This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.
This volume contains 12 sessions, 28 papers and 26 presentations on the following topics: Photonic Integrated Circuits and Plasmonic Sensing; Advancs in CBE Signature Modeling and Sensor Algorithms I; Standoff Sensing of CBRNE Hazards I; Standoff Sensing of CBRNE Hazards II; Advances in CBE Signature Modeling and Sensor Algorithms II; Biological Hazard Sensing; Chemical Hazard Sensing; Joint Session with Conferences 11390 and 11416: Spectroscopy for CBRNE Detection and Warning; Radiological and Nuclear Sensing; Explosive Material Sensing; Poster Session.