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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 775 records · Page 43
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Monolithic CCD-array readout

Circuit is self-biasing, with differential current-to-voltage conversion. CMOS current-differencing readout consists of dc-balanced pair of virtual ground stages and current-differencing circuit similar to circuit mirror. Triode multiplier cell replaces test sources to form monolithic configuration. Transistors belonging to selected multiplier cell need to be duplicated for each multiplier within correlator chip. Remaining elements form part of readout and may be scaled as single common readout stage.

Farnsworth, D. L.↗
NASA NTRS1980

Low power NASA 36 bit time code generator

A 36 bit time code generator implemented in CMOS is described. A microprocessor is used to minimize chip count. A modified 20 second format is available as an option, by changing two program steps.

Langjahr, D.↗
NASA NTRS1978

Characterization and modeling of radiation effects NASA/MSFC semiconductor devices

A literature review of the near-Earth trapped radiation of the Van Allen Belts, the radiation within the solar system resulting from the solar wind, and the cosmic radiation levels of deep space showed that a reasonable simulation of space radiation, particularly the Earth orbital environment, could be simulated in the laboratory by proton bombardment. A 3 MeV proton accelerator was used to irradiate CMOS integrated circuits fabricated from three different processes. The drain current and output voltage for three inverters was recorded as the input voltage was swept from zero to ten volts after each successive irradiation. Device parameters were extracted. Possible damage mechanisms are discussed and recommendations for improved radiation hardness are suggested.

Kerns, D. V., Jr.↗
NASA NTRS1979

NASA AMES infrared detector assemblies

Silicon: Gallium infrared detector assemblies were designed, fabricated, and tested using techniques representative of those employed for hybrid arrays to determine the suitability of this candidate technology for infrared astronomical detector array applications. Both the single channel assembly and the assembly using a 32 channel CMOS multiplexer are considered. The detector material was certified to have a boron background of less than 10 to the 13th power atoms/sq cm counter doped with phosphorus. The gallium concentration is 2 x 10 to the 16th power atoms/cu cm.

Source record↗
NASA NTRS1981

RAD hard PROM design study

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

Source record↗
NASA NTRS1980

A study of single event upsets in static RAM's

Several types of CMOS static random access memories (RAMs) have been tested in a cyclotron for susceptibility to single event upsets and latchup such as might occur in earth orbit or interplanetary space. No upsets have been observed for neutron fluences of 10 to the 11th n/sq cm and higher or proton fluences of 10 to the 9th protons/sq cm.

Price, W. E.↗
NASA NTRS1981

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Barrett, W. J.↗
NASA NTRS1981

Automatic arc welding of propulsion system tubing in close proximity to sensitive electronic devices

The planned final assembly of the Galileo spacecraft propulsion system tubing, which involves welding in close proximity to sensitive electronics, raised significant concerns about the effects of electromagnetic coupling of weld energy on CMOS and other sensitive integrated circuits. A test program was established to assess the potential of an orbital arc welder and an RF-induction brazing machine to damage sensitive electronic equipment. Test parameters were varied to assess the effectiveness of typical transient suppression practices such as grounding, bonding, and shielding. A technique was developed to calibrate the hazard levels at the victim-circuit location; this technique is described along with the results and conclusions of the test program.

Lumsden, J. M.↗
NASA NTRS1983

Portable I/V-Curve Tester

Electronic load circuit for displaying current/voltage characteristic curves of power sources uses low-cost low-power CMOS operational amplifiers to control load current flowing through power MOSFET Q2 and main load transistor Q3. Thermal cutoff device turns off transistor Q3 in case of overload. To maximize battery life, battery is connected via "push-to-read" momentary-contact pushbutton switch.

Cole, S. W.↗
NASA NTRS1983

Solid State Circuits for Cryogenic Operation

Tests confirm operation of five commercial semiconductor devices at cryogenic temperatures. The five devices - one tunnel diode, one field-effect transistor, and three CMOS integrated circuits - all perform well in circuits immersed in liquid-helium bath. For some tests, bath temperature was reduced to 1,25K by pumping.

Petrac, D.↗
NASA NTRS1981

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Source record↗
NASA NTRS1981

Architecture for VLSI design of Reed-Solomon encoders

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.↗
NASA NTRS1982

Architecture for VLSI design of Reed-Solomon encoders

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Liu, K. Y.↗
NASA NTRS1984

The Effect of Cosmic Rays on MSI Devices

Low-power devices susceptible to cosmic-ray particles. Five MSI device technologies, including TTL, low power TTL, Schottky, CMOS, and low-power Schottky, subjected to 120-MeV krypton-ion beam from cyclotron and monitored for single-event upset. Results find terrestrial application for radiation hardening of electronic devices and systems.

Nichols, D. K.↗
NASA NTRS1984

Optical Testing of Integrated Circuits

Optical spot-raster scanner produces weighted photoresponse image (PI) of operating CMOS IC. Digital analysis of PI's, which correlates differences in PI's with electrical behavior of IC, shows promise both as 100-percent screening method for use in IC manufacture and as diagnostic tool in IC development.

Erickson, J.↗
NASA NTRS1984

Detection of Floating Inputs in Logic Circuits

Simple modification of oscilloscope probe allows easy detection of floating inputs or tristate outputs in digital-IC's. Oscilloscope probe easily modified with 1/4 W resistor and switch for detecting floating inputs in CMOS logic circuits.

Cash, B.↗
NASA NTRS1981

Memory technology survey

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

Source record↗
NASA NTRS1983

RS-232 communications analyzer module for HP-1602A logic analyzer

The design and construction of a simple ASCII analyzer is described. It was built to interface directly to a Hewlett-Packard 1602A logic state analyzer but the circuitry could easily be configured to operate with any logic analyzer. The design of the ASCII analyzer allows the use of all the trace and delay functions for the HF-1602A. The ASCII analyzer circuit utilizes two universal Asynchronous Receiver/Transmitters (UAR/Ts) to simultaneously examine both the transmit and receive serial data lines. Baud rates from 300 to 9600 bits per second are selectable with the externally mounted DIP switch. The unit requires no external power supply connection and all of the integrated circuits are CMOS for low power consumption.

Yost, S. R.↗