Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “integrated circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 739 records · Page 41
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2008

Integrator Circuitry for Single Channel Radiation Detector

Input circuitry is provided for a high voltage operated radiation detector to receive pulses from the detector having a rise time in the range of from about one nanosecond to about ten nanoseconds. An integrator circuit, which utilizes current feedback, receives the incoming charge from the radiation detector and creates voltage by integrating across a small capacitor. The integrator utilizes an amplifier which closely follows the voltage across the capacitor to produce an integrator output pulse with a peak value which may be used to determine the energy which produced the pulse. The pulse width of the output is stretched to approximately 50 to 300 nanoseconds for use by subsequent circuits which may then use amplifiers with lower slew rates.

Holland, Samuel D.↗
NASA NTRS2009

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy↗
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS2001

Coupling between Microstrip Lines Embedded in Polyimide Layers for 3D-MMICs on Si

Three-dimensional circuits built upon multiple layers of polyimide are required for constructing SilSiGe monolithic microwavdmillimeter-wave integrated circuits on CMOS (low resistivity) Si wafers. However, the closely spaced transmission lines are susceptible to high levels of coupling, which degrades circuit performance. In this paper, Finite Difference Time Domain (FDTD) analysis and measured characteristics of novel shielding structures that significantly reduce coupling between embedded microstrip lines are presented. A discussion of the electric and magnetic field distributions for the coupled microstrip lines is presented to provide a physical rationale for the presented results.

Ponchak, George E.↗
NASA NTRS2009

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Samoska, Lorene↗
NASA NTRS2011

Circuit for Communication Over Power Lines

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

Krasowski, Michael J.↗
NASA NTRS1979

Miniature Ku-Band down converter

Hybrid circuit serves as receiver front end for 13.75- to 14.0-GHz communications and radar systems. Complete microwave integrated circuit (MIC) assembly is packaged in small hermetically welded, nitrogen-filled aluminum case. Simplicity and size proves useful for lower-frequency wideband applications.

Norbury, D. A.↗
NASA NTRS1980

Inductorless tuned circuit for high frequencies

Inductorless tuned circuit functions as filter, amplifier, or oscillator at radio frequencies. Circuit is based on two directly-coupled transistors operated at their transition frequency and fabricated as integrated circuit on single silicon chip.

Kleinberg, L.↗
NASA NTRS1985

A VHSIC general purpose processor

The very high speed integrated circuit (VHSIC) program offers NASA and its contractors assured availability of military specification embedded computer components and integrated computer aided design/computer aided engineering and software development support that result in low system life costs for data management systems on the space station and the Earth Observatory Satellite. Viewgraphs given review progress in both the Department of Defense VHSIC program and the NASA VHSIC related insertion development of a general purpose processor are presented.

Benz, H. F.↗
NASA NTRS1996

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Langenbacher, Harry T.↗
NASA NTRS1996

Micromachined Ion Accelerators

Proposed ion accelerators made by micromachining techniques. Advantages include small size and weight, modularity, and compatibility with integrated circuits. Used as sources of ion beams for industrial processes. Ion accelerator of this type combined with integrated electronic control and power circuitry, plus similarly miniaturized valves and other mechanisms for regulating flow of gas used to generate ions - all micromachined on single chip. Provides flexibility for tailoring characteristics of ion sources for specific applications; for example, construct array of many such devices to obtain large ion source or position multiple devices to obtain desired ion-beam pattern in processing chamber.

Brophy, John↗
NASA NTRS2012

Single-Pole Double-Throw MMIC Switches for a Microwave Radiometer

In order to reduce the effect of gain and noise instabilities in the RF chain of a microwave radiometer, a Dicke radiometer topology is often used, as in the case of the proposed surface water and ocean topography (SWOT) radiometer instrument. For this topology, a single-pole double-throw (SPDT) microwave switch is needed, which must have low insertion loss at the radiometer channel frequencies to minimize the overall receiver noise figure. Total power radiometers are limited in accuracy due to the continuous variation in gain of the receiver. High-frequency SPDT switches were developed in the form of monolithic microwave integrated circuits (MMICs) using 75 micron indium phosphide (InP) PIN-diode technology. These switches can be easily integrated into Dicke switched radiometers that utilize microstrip technology.

Montes, Oliver↗
NASA NTRS1991

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗
NASA NTRS2003

164-GHz MMIC HEMT Frequency Doubler

A monolithic microwave integrated circuit (MMIC) that includes a high-electron-mobility transistor (HEMT) has been developed as a prototype of improved frequency doublers for generating signals at frequencies greater than 100 GHz. Signal sources that operate in this frequency range are needed for a variety of applications, notably including general radiometry and, more specifically, radiometric remote sensing of the atmosphere. Heretofore, it has been common practice to use passive (diode-based) frequency multipliers to obtain frequencies greater than 100 GHz. Unfortunately, diode-based frequency multipliers are plagued by high DC power consumption and low conversion efficiency. Moreover, multiplier diodes are not easily integrated with such other multiplier-circuit components as amplifiers and oscillators. The goals of developing the present MMIC HEMT frequency doubler were (1) to utilize the HEMT as an amplifier to increase conversion efficiency (more precisely, to reduce conversion loss), thereby increasing the output power for a given DC power consumption or, equivalently, reducing the DC power consumption for a given output power; and (2) to provide for the integration of amplifier and oscillator components on the same chip. The MMIC frequency doubler (see Figure 1) contains an AlInAs/GaInAs/InP HEMT biased at pinch-off to make it function as a class-B amplifier (meaning that it conducts in half-cycle pulses). Grounded coplanar waveguides (GCPWs) are used as impedance-matching transmission lines. Air bridges are placed at discontinuities to suppress undesired slot electromagnetic modes. Another combination of GCPWs also serves both as a low-pass filter to suppress undesired oscillations at frequencies below 60 GHz and as a DC blocker. Large decoupling capacitors and epitaxial resistors are added in the drain and gate lines to suppress bias oscillations. At the output terminal, the fundamental frequency is suppressed by a quarter-wave open stub, which presents a short circuit at the fundamental frequency and an open circuit at the second harmonic. At an input power of 7 mW, the output power and conversion loss at an output frequency of 164 GHz were found to be 5 dBm (approximately equal to 3.2 mW) and 2 dB, respectively, with a 3-dB output-power bandwidth of 14 GHz. This is the best performance reported to date for an MMIC HEMT frequency doubler above 100 GHz.

Samoska, Lorene↗
NASA NTRS1979

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

Mcgrady, W. J.↗
NASA NTRS1995

Advanced packaging for Integrated Micro-Instruments

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Lyke, James L.↗