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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 739 records · Page 41
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Power MOSFET and JBSFET cell topologies with superior high frequency figure of merit

A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

Baliga, Bantval Jayant↗
DOE OSTI2023

Three dimensional vertically structured electronic devices

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Conway, Adam↗
DOE OSTI2020

2D Dam-Break Analysis of L Lake and PAR Pond Dams Using HEC-RAS

In 1991 a dam-break study was conducted for the high hazard dams located at L Lake and PAR Pond on the Savannah River Site. Two scenarios were considered, over topping from a Probable Maximum Flood (PMF), and a fair weather dam-break for either or both dams. Unfortunately, no inundation map was developed from the study. The purpose of this project was to redo the original dam-break study with improved data and methodology to generate Inundation maps to assist with emergency response and evacuation plans. The Hydrologic Engineering Center's River Analysis System (HEC-RAS) is a free to download river analysis modeling program developed by the US Army Corps of Engineers capable of 1D and 2D hydraulic calculations. Version 5.0.7 (released March 2019) was used for this project. Digital elevation models for the area were retrieved from the US Geological Survey database and converted to a .hdf file within the program. Then the 2D flood area was identified from the contours. Both L Lake and PAR Pond were inputted as 1D storage areas because DEM data does not contain elevation values under water bodies. An elevation vs volume curve was available for both storage areas. Initial elevations were set for both scenarios. Both dams are earthen dams. The Steel Creek dam at L Lake has 6 ft diameter conduit with an upper and lower sluice gate. PAR pond dam consist of a weir and sluice gate connected to an 8 x 8 ft channel. Both outlets were modeled with a pool elevation vs discharge curve. The steel creek dam sluice gates were assumed to be fully open in all cases. As in the previous study, the dams were set to breach when they were overtopped by 1.5 ft during PMF conditions (Figure 1). A fair weather breach was set to be due to a piping failure (Figure 1). In the dual dam break during fair weather conditions the PAR pond dam fails 3 hours after Steel Creek to achieve maximum flooding in the down stream reaches. Simulation was run 3 days for each case and with a 1 minute computational interval. Maximum flooding occurs under PMF conditions with the failure of both dams. PAR pond dam fails first 16 hours and 32 minutes after the start of the simulation with the Steel creek dam failing 6 minutes later. In all cases, the bridges and roads spanning Steel Creek and Lower Three Runs will be inundated and potentially washed away. The Burtons Ferry Highway south of the storage areas will be partially flooded during PMF failure, dual fair weather failure, and PAR pond failure under fair weather conditions.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗
DOE OSTI2024

Simulating single qubit RB

Single qubit RB is used to measure the error of gates via average gate fidelity. A single qubit RB program was made to calculate this. To filter out potential hardware issues, RB was executed through creating a simulator. Upon simulating both noisy and noise-less gates, we determined that there is a mix of hardware and program issues.

Anguiano, Efren↗
DOE OSTI2024

Power Module Precursors and Prognostics

This project focuses on finding and utilizing electrical properties (precursors) of power electronic devices and modules whose changes have strong correlations with different modes and levels of degradations in order to realize online and lightweight state of health evaluation and fault diagnosis. Results from this project will contribute to higher safety, reliability, and power density of power electronic components. The approaches mainly include reviewing academic literature and industry practices for state of the art precursor identification and extraction, accelerated life cycles (ALC) of various power modules to create different degradations in-house, and developing techniques for gate-driver-integratable precursor detection circuit. In FY24, the results includes two sets of definitively detected aging precursors (on-state resistance and gate threshold voltage) for two sets of power modules respectively, controlled accelerated lifetime cycling of multiple silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and the development and validation of a gate voltage detection system.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2026

Universal monitored dynamics in multimode bosonic systems

We propose a route to study monitored many-body dynamics in multimode bosonic systems using circuit quantum electrodynamics. In this experimental setting, we construct several bosonic models comprising brickwork circuits built from beam-splitter gates, local parity measurements, and optional on-site Hubbard interactions, and diagnose their monitored dynamics via ancilla purification and a learnability-based probe. Under parity measurements, generic gate sets exhibit behavior that is largely consistent with a conventional measurement-induced phase transition, while a special class of beam-splitter circuits shows an apparent critical-like high-measurement regime in which purification times scale linearly with system size. We show that for realistic noise, gate, and measurement rates, these signatures are observable with near-term circuit QED hardware.

Patel, Shivam [Rutgers U., Piscataway]↗
DOE OSTI2023

Distributed Quantum Computing with Photons and Atomic Memories

The promise of universal quantum computing requires scalable single- and inter-qubit control interactions. Currently, three of the leading candidate platforms for quantum computing are based on superconducting circuits, trapped ions, and neutral atom arrays. However, these systems have strong interaction with environmental and control noises that introduce decoherence of qubit states and gate operations. Alternatively, photons are well decoupled from the environment and have advantages of speed and timing for quantum computing. Photonic systems have already demonstrated capability for solving specific intractable problems like Boson sampling, but face challenges for practically scalable universal quantum computing solutions because it is extremely difficult for a single photon to “talk” to another deterministically. Here, a universal distributed quantum computing scheme based on photons and atomic-ensemble-based quantum memories is proposed. Taking the established photonic advantages, two-qubit nonlinear interaction is mediated by converting photonic qubits into quantum memory states and employing Rydberg blockade for the controlled gate operation. Spatial and temporal scalability of this scheme is demonstrated further. Furthermore, these results show photon-atom network hybrid approach can be a potential solution to universal distributed quantum computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Power Module Precursors and Prognostics

The ongoing work involves 1) the identification and evaluation of various electric signals as indicators to module failure and precursors to aging, and 2) the development of corresponding detection techniques. In the current phase, 1) the increase of on-state resistance is selected as the precursor to the power cycle aging of silicon carbide power MOSFET modules based on review and rest data. 2) A detection method leveraging the gate voltage fluctuations magnitude during commutation transients to inform the on-state resistance increase is investigated which has the benefit of being able to be integrated into the gate driver. A dedicated detection circuit for implementation is designed and simulated and is currently in fabrication.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2026

Maximizing dynamic range and performance of anatase TiO 2 ECRAM through structure and programming

Here, in this study, we investigate the structure-dependent modulation characteristics of all-solid-state three-terminal electrochemical random-access memory (ECRAM) based on an anatase Li x TiO 2 channel. By directly comparing “asymmetric” and “symmetric” ECRAM device architectures, we reveal significant insight into the impact of a non-zero gate-drain open-circuit voltage and its influence on voltage vs. current-controlled gating. We also explore the impact of potentiation/depression write parameters on the symmetry, linearity, and dynamic range of the device response. Together, initial results from optimizing structure and programming approaches yielded unprecedented G max /G min ratios of >1,000 for ECRAM and hundreds of tunable memory states with excellent linearity and symmetry. Simulations based on these ECRAM devices further illustrate the promise of this analog memory technology, achieving near 2% classification error in the MNIST digit recognition benchmark for a range of training parameters compared to a theoretical best of 1.66% and outperforming other device models extracted from the literature.

AIHWKit↗
DOE OSTI2022

The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectors

We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of ℱ avg =99.93%. All of the schematics, firmware, and software are open-source.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Shifting agricultural practices to produce sustainable, low carbon intensity feedstocks for biofuel production

The carbon intensity (CI) of biofuel's well-to-pump life cycle is calculated by life cycle analysis (LCA) to account for the energy/material inputs of the feedstock production and fuel conversion stages and the associated greenhouse gas (GHG) emissions during these stages. The LCA is used by the California Air Resources Board's Low Carbon Fuel Standard (LCFS) program to calculate CI and monetary credits are issued based on the difference between a given fuel's CI and a reference fuel's CI. Through the Tier 2 certification program under which individual fuel production facilities can submit their own CIs with their facility input data, the LCFS has driven innovative technologies to biofuel conversion facilities, resulting in substantial reductions in GHG emissions as compared to the baseline gasoline or diesel. A similar approach can be taken to allow feedstock petition in the LCFS so that lower-CI feedstock can be rewarded. Here we examined the potential for various agronomic practices to improve the GHG profiles of corn ethanol by performing feedstock-level CI analysis for the Midwestern United States. Our system boundary covers GHG emissions from the cradle-to-farm-gate activities (i.e. farm input manufacturing and feedstock production), along with the potential impacts of soil organic carbon change during feedstock production. We conducted scenario-based CI analysis of ethanol, coupled with regionalized inventory data, for various farming practices to manage corn fields, and identified key parameters affecting cradle-to-farm-gate GHG emissions. The results demonstrate large spatial variations in CI of ethanol due to farm input use and land management practices. In particular, adopting conservation tillage, reducing nitrogen fertilizer use, and implementing cover crops has the potential to reduce GHG emissions per unit corn produced when compared to a baseline scenario of corn–soybean rotation. This work shows a large potential emission offset opportunity by allowing feedstock producers a path to Tier 2 petitions that reward low-CI feedstocks and further reduce biofuels' CI. The prevalence of significant acreage that has not been optimized for CI suggests that policy changes that incentivize optimization of this parameter could provide significant additionality over current trends in farm efficiency and adoption of conservation practice.

09 BIOMASS FUELS↗
DOE OSTI2022

Engineering, Control, and Longitudinal Readout of Floquet Qubits

We discuss how properties of time-periodic Hamiltonians can be exploited to increase the dephasing time of qubits and to design protected one- and two-qubit gates. Recently, Huang et al. [Phys. Rev. Applied 15, 034065 (2021)] have shown that Floquet states offer a manifold of working points with dynamical protection larger than the few, usual, static sweet spots. Here, we show how Floquet theory, often used on systems with a single drive tone, can be used to describe approaches to robustly control Floquet qubits in the presence of multiple commensurate drive tones. Using this formulation, we introduce a longitudinal readout protocol to measure the Floquet qubit without the need of first adiabatically mapping the Floquet states back to the static qubit states, resulting in a significant speedup in the measurement time of the Floquet qubit. The analytical approach developed here can be applied to any Hamiltonian involving a small number of distinct drive tones, typical in the study of standard parametric gates for qubits outside of the rotating-wave approximation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Spin dynamics in quantum dots on liquid helium

Liquid He-4 is free from magnetic defects, making it an ideal substrate for electrons with long-lived spin states. Such states can serve as qubit states. Here, in this study, we consider the spin states of electrons electrostatically localized in quantum dots on a helium surface. Efficient gate operations in this system require spin-orbit coupling. It can be created by a nonuniform magnetic field from a current-carrying wire, can be turned on and off, and allows one to obtain large electrodipole moment and comparatively fast coupling of spins in neighboring dots. Of central importance is to understand spin decay due to the spin-orbit coupling. We establish the leading mechanism of such decay and show that the decay is sufficiently slow to enable high-fidelity single- and two-qubit gate operations.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Qutrit Randomized Benchmarking

Ternary quantum processors offer significant potential computational advantages over conventional qubit technologies, leveraging the encoding and processing of quantum information in qutrits (three-level systems). Therefore, to evaluate and compare the performance of such emerging quantum hardware it is essential to have robust benchmarking methods suitable for a higher-dimensional Hilbert space. We demonstrate extensions of industry standard randomized benchmarking (RB) protocols, developed and used extensively for qubits, suitable for ternary quantum logic. Using a superconducting five-qutrit processor, we find an average single-qutrit process infidelity of 3.8×10 -3 . Through interleaved RB, we characterize a few relevant gates, and employ simultaneous RB to fully characterize crosstalk errors. Finally, we apply cycle benchmarking to a two-qutrit CSUM gate and obtain a two-qutrit process fidelity of 0.85. Our results present and demonstrate RB-based tools to characterize the performance of a qutrit processor, and a general approach to diagnose control errors in future qudit hardware.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Efficient Unitary Designs from Random Sums and Permutations

A unitary k-design is an ensemble of unitaries that matches the first k moments of the Haar measure. In this work, we provide two efficient constructions of k-designs on n-qubits using new random matrix theory techniques. Our first construction is based on exponentiating sums of random i.i.d. Hermitian matrices and uses O(k2n2)-many gates. In the spirit of central limit theorems, we show that this random sum approximates the Gaussian Unitary Ensemble (GUE). We then show that the product of just two exponentiated GUE matrices is already approximately Haar random. Our second construction is based on products of exponentiated sums of random permutations and uses Õ(k poly (n)) many gates. The k dependence is optimal (up to polylogarithmic factors) and is inherited from the efficiency of existing k-wise independent permutations. Furthermore, replacing random permutations with quantum-secure pseudorandom permutations (PRPs), we also obtain a pseudorandom unitary (PRU) ensemble that is secure under nonadaptive queries. A central feature of both proofs is a new connection between the polynomial method in quantum query complexity and the large-dimension (N) expansion in random matrix theory. In particular, the first construction uses the polynomial method to control high moments of certain random matrix ensembles without requiring delicate Weingarten calculations. In doing so, we define and solve a moment problem on the unit circle, asking whether a finite number of equally weighted points can reproduce a given set of moments. In our second construction, the key step is to exhibit an orthonormal basis for irreducible representations of the partition algebra that has a low-degree large-N expansion. This allows us to show that the distinguishing probability is a low-degree rational polynomial of the dimension N.

algebra↗
DOE OSTI2024

The Effects of Threshold Voltage and Number of Fins per Transistor on the TID Response of GF 12LP Technology

This abstract presents a comprehensive analysis of total ionizing dose (TID) response in GlobalFoundries’ 12LP 12nm bulk FinFET technology using 10keV X-rays. Devices with higher threshold voltages (VTs) demonstrated lower increases in off-state leakage current (IDS,OFF) post-irradiation, highlighting the mitigating role of high VT in TID response. Our data shows that transistors with fewer fins exhibit superior TID resistance, implying lower susceptibility to radiation effects. Our study also probed two bias conditions, "Gate-On" and "Pass-Gate," with the former displaying more severe TID degradation. Interestingly, p-type devices displayed negligible degradation, underscoring their inherent resilience to TID effects. Additionally, medium thick n-type devices echoed the fin-count-dependent TID response observed in other transistor types, further strengthening our findings. These results underscore the importance of strategic transistor selection and design for enhancing the TID resilience of future CMOS FinFET architectures, particularly critical in radiation-intense environments.

42 ENGINEERING↗
DOE OSTI2021

Hardware Design of Medium Voltage SiC-Based Modular Multilevel Converters for Grid-Tied Applications

This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.

auxiliary power supply↗