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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

NASA NTRS1980

Investigation of multilayer magnetic domain lattice file

The feasibility of the self structured multilayered bubble domain memory as a mass memory medium for satellite applications is examined. Theoretical considerations of multilayer bubble supporting materials are presented, in addition to the experimental evaluation of current accessed circuitry for various memory functions. The design, fabrication, and test of four device designs is described, and a recommended memory storage area configuration is presented. Memory functions which were demonstrated include the current accessed propagation of bubble domains and stripe domains, pinning of stripe domain ends, generation of single and double bubbles, generation of arrays of coexisting strip and bubble domains in a single garnet layer, and demonstration of different values of the strip out field for single and double bubbles indicating adequate margins for data detection. All functions necessary to develop a multilayer self structured bubble memory device were demonstrated in individual experiments.

Torok, E. J.↗

NASA NTRS1973

Tetrad bubble domain chip arrangement for multiplexing

Rotating magnetic field of bubble domain memory is used to obtain time-division multiplexing of bubble domain circuits into quadrants. Memory bits are assigned on bit-per-chip rather than bit-per-module basis; power is reduced by circulating only portion of bubbles at a time.

Almasi, G. S.↗

NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

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NASA NTRS1987

Computers in Spaceflight: the NASA Experience

This book examines the computer systems used in actual spaceflight or in close support of it. Computer systems used in administration and in aeronautical and other research not directly related to spaceflight are ignored. Each chapter deals with either a specific program, such as Gemini or Apollo onboard computers, or a closely related set of systems, such as launch processing or mission control.. A glossary of computer terms is included.

assembly language↗

NASA NTRS1972

Investigation of single crystal ferrite thin films

Materials suitable for use in magnetic bubble domain memories were developed for aerospace applications. Practical techniques for the preparation of such materials in forms required for fabrication of computer memory devices were considered. The materials studied were epitaxial films of various compositions of the gallium-substituted yttrium gadolinium iron garnet system. The major emphasis was to determine their bubble properties and the conditions necessary for growing uncracked, high quality films.

Mee, J. E.↗

NASA NTRS1975

Processor architectures utilizing magnetic bubble and semi-conductor memories

To aid work being conducted on the feasibility of a low cost Omega navigational receiver, a control panel was designed and constructed according to supplied specifications. Since the proposed Omega receiver is designed around a microprocessor, software engineering necessary for control panel operation is included in the design. The control panel is to be used as an operational model for use in the design of a prototype receiver. A detailed description of the hardware design is presented along with a description of the software needed to operate the panel. A complete description of the operating procedures for the panel are also included.

Parrish, E. A., Jr.↗

NASA NTRS1977

Bridge/amplifier configuration for switched arrays

Bridge network connected to differential amplifier and used with bubble-domain memories draws no power during standby and can be arrayed with other bridge amplifiers of like design. Two-node arrangement greatly simplifies conventional configurations where more than two nodes are involved.

Bohning, O. D.↗

NASA NTRS1980

A spacecraft mass memory design using self-structured magnetic bubbles

A self-structured multilayered bubble device developed for spacecraft sensor systems is described. The data link buffer mass memory is analyzed, and system characteristics are estimated based on a nominal 1.6 micron bubble diameter. It is shown that a memory of at least 10 billion bits capacity and 30 megabits per second could be developed with conventional spacecraft constraints.

Stermer, R. L., Jr.↗

NASA NTRS1977

Packaging of a large capacity magnetic bubble domain spacecraft recorder

A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply.

Becker, F. J.↗

NASA NTRS1994

Partial-Thickness Grooves In A VBL Memory Device

Bias magnetic fields tailored to match those needed elsewhere in device. Grooves through part of thickness of magnetic garnet storage layer of vertical-Bloch-line (VBL) memory device used to confine magnetic bubble and stripe domains in desired storage areas. VBL-memory concept described in "Vertical-Bloch-Line Memory" (NPO-18467).

Katti, Romney R.↗

NASA NTRS1978

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Hayes, P. J.↗

NASA NTRS1985

Compatible atmospheres for a space suit, Space Station, and Shuttle based on physiological principles

Fundamental physiological principles have been invoked to design compatible environments for a space suit, Space Station and the spacecraft used to transport the astronauts from earth. These principles include the long-term memory of tissues for a bubble-provoking decompression, the intermittent nature of blood flow in the tight connective tissue(s) responsible for the bends whose incidence in aviators has been shown to be related to bubble volume by the Weibull distribution. In the overall design an astronaut breathing a mixture of 30 percent O2 in N2 for 4-5 h in a spacecraft at 11.9 psia can transfer to a Space Station filled with the same mix at 8.7 psia and, after a further 4-5 h, go EVA at any time without any oxygen prebreathing at any stage. The probable incidence of decompression sickness has been estimated as less than 0.5 percent using the present suit operating at 4.3 psia but the risk could be reduced to zero if the suit pressure were increased to 6.5 psia.

Hills, B. A.↗

NASA NTRS1981

Memory technology survey

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

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NASA NTRS1977

A passive chevron replicator

Instrument design provides replicate function between device storage area and guardrail detector in order that nondestructive read-out of memory can be achieved. Use of guardrail detectors in magnetic domain (bubble) circuits is proposed method of increasing detector signal output by increasing detector size without dedicating an excessive amount of device chip area to detector portion.

Oeffinger, T. R.↗

NASA NTRS1991

Major line operation in vertical Bloch line memory

An experimental and numerical study is conducted of the operation of a major line in a vertical Bloch-line memory that employs a partial garnet-grooving architecture and contains (1) a bubble generator; (2) a bubble-propagation track; (3) a bubble-expander for detection; and (4) a bubble annihilator. The bubble expander is a modification of the propagation track; the meandering conductor and groove width were gradually increased to stretch the bubble into a stripe. The numerical model employed encompasses the garnet-grooving effect. Agreement is obtained between exparimental and simulation results.

Wu, J. C.↗

NASA NTRS1972

Trends in solid state electronics, part 2

Developments in the fields of semiconductors and magnetics are surveyed. Materials, devices, theory, and fabrication technology are discussed. Important events up until the present time are reported, and events are interpreted through historical perspective. A brief analysis of forces which have driven the development of today's electronic technology and some projections of present trends are given. More detailed discussions are presented for four areas of contemporary interest: amorphous semiconductors, bubble domain devices, charge-coupled devices, and electron and ion beam techniques. Beam addressed magnetic memories are reviewed to a lesser extent.

Gassaway, J. D.↗

NASA NTRS1995

Vertical bloch line memory

A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Katti, Romney R.↗

NASA NTRS1978

A solid state data recorder for spacecraft telemetry applications

A solid state data recorder (SSDR) has been developed which offers a high-reliability alternative to tape recorders in many spacecraft telemetry applications. The storage medium used in this recorder was ferrimagnetic garnet films supporting nonvolatile magnetic bubble domains. The recorder was designed using modular construction consisting of a digital control unit, power supply, and two memory modules. A prototype SSDR has been fabricated which is designed for 100-million bits of storage but was populated with 128 chips for a 13-million bit capacity. Preliminary tests indicate satisfactory operation.

Stermer, R. L., Jr.↗