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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 667 records · Page 37
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

Buehler, M.↗
NASA NTRS2009

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

MacLeod, Todd C.↗
NASA NTRS1986

Metalization Patterns by Thermal Decomposition

Metal interconnection pattern deposited on integrated circuit or solar cell economically by thermal decomposition of metallo-organic compound. In proposed process beam from laser or quartz lamp swept over substrate in required metalization pattern; wherever beam impinges on substrate, radiant heat decomposes compound, depositing metal. Process requires less costly equipment and less time than conventional metalization. Process readily adaptable to very-large-scale integrated (VLSI) circuits.

Gallagher, B. D.↗
NASA NTRS2006

Towards Terahertz MMIC Amplifiers: Present Status and Trends

This viewgraph presentation surveys the fastest Monolithic Millimeter-wave Integrated Circuit (MMIC) amplifiers to date; summarize previous solid state power amp results to date; reviews examples of MMICs, reviews Power vs. Gate periphery and frequency; Summarizes previous LNA results to date; reviews Noise figure results and trends toward higher frequency

FET ampllifiers↗
NASA NTRS2008

Embedded ESD Protection Proof of Concept

The purpose of this project is to characterize and correlate Electrostatic Discharge (ESD) sensitivity levels of an Integrated Circuit (IC) package using Transmission Line Pulse (TLP) and Human Body Model (HBM) methods. This characterization will be used as a baseline ESD sensitivity level to demonstrate improvement to the ESD sensitivity of the IC package through the use of EPI-FLO(Trade Mark) Polymer Voltage Suppression (PVS) protection devices developed and manufactured by Electronic Polymers, Inc. (EPI).

Human Body Model (HBM) methods↗
NASA NTRS2023

Processing Choices for Achieving Long Term IC Operation at 500° C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

SiC, JFET, Integrated Circuits, High-Temperature, ↗
NASA NTRS2018

Room Temperature Total-Ionizing Dose Testing of Glenn Research Center (GRC) 500 °C Durable 4H-SiC JFET IC Technology

The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.

Radiation↗
NASA NTRS2005

Medium power amplifiers covering 90 - 130 GHz for telescope local oscillators

This paper describes a set of power amplifier (PA) modules containing InP High Electron Mobility Transistor (HEMT) Monolithic Millimeter-wave Integrated Circuit (MMIC) chips. The chips were designed and optimized for local oscillator sources in the 90-130 GHz band for the Atacama Large Millimeter Array telescope. The modules feature 20-45 mW of output power, to date the highest power from solid state HEMT MMIC modules above 110 GHz.

coplanar waveguides↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS2016

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

high temperature↗
NASA NTRSDate not supplied

Multi-Gbps Fiber-Optic Wavefront Sensing Coherent Optical Receiver

We report recent progress on technology developments at the NASA Glenn Research Center using photonic lanterns for coherent optical communications applications. In particular, the development of a spatial mode-diversity optical receiver using a photonic lantern combined with a photonic integrated circuit (PIC). The PIC is designed for compatibility with the NASA Laser Communication Relay Demonstration’s (LCRD) differential phase-shift keying signaling format. We report on the PIC design and future characterization and packaging efforts. Additionally, we report on the development of a 19-channel photonic lantern and provide updates on efforts to use the photonic lantern as a wavefront sensing device. The photonic lantern insertion loss, and spatial-mode transfer characteristics are detailed, as well as the development of a predictive framework in which the intensities in the 19 single-mode output channels are used to reconstruct the wavefront of the light entering the multi-moded input side of the lantern. Finally, we discuss concepts for potential future systems using photonic lanterns and PICs that combine both wavefront sensing and coherent communications onto a single integrated platform.

Optical Communications↗
NASA NTRS2005

Beyond G-band : a 235 GHz InP MMIC amplifier

We present results on an InP monolithic millimeter- wave integrated circuit (MMIC) amplifier having 10-dB gain at 235 GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technology's (NGST) 0.07- m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325 GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for -parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230 GHz.

high electron mobility transistors (HEMTs)↗
NASA NTRS2013

A 75-116-Ghz LNA with 23-K Noise Temperature at 108 Ghz

In this paper we present the design and measurement results, both on-wafer and in package, of an ultra-low-noise and wideband monolithic microwave integrated circuit (MMIC) amplifier in the frequency range of 75 to 116 GHz. The three-stage amplifier packaged in a WR10 waveguide housing and fabricated using a 35-nm InP HEMT technology achieves a record noise temperature of 23 K at 108 GHz when cryogenically cooled to 27 K. The measured gain is 22 to 27 dB for frequency range of 75 to 116 GHz. Furthermore, the amplifier utilizes four finger devices with total gate width of 60 um resulting for improved linearity.

monolithic microwave integrated circuit (MMIC)↗
NASA NTRS2018

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460 °C, ~9.3 MPa (~ 92 Earth atmospheres) chemically reactive environment. Here we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost 3-fold and were accomplished using prototype SiC JFET chips of more than 7-fold increased complexity. The demonstrated advancement marks a significant step towards realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Integrated Circuit↗
NASA NTRS2003

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

infrared↗
NASA NTRS1998

Finite Ground Coplanar (FGC) Waveguide: A Better Transmission Line for Microwave Circuits

A new version of coplanar waveguide (CPW) with electrically narrow ground strips 14 has been developed for microwave integrated circuits. This transmission line, referred to by Finite Ground Coplanar (FGC) waveguide, has several advantages over conventional coplanar waveguide. Since the ground strips are narrow, parasitic resonances that develop when the CPW is placed on a carrier or in a package are eliminated. In addition, the narrow ground strips permit the integration of lumped and distributed circuit elements in the ground strips as well as in the center strip to reduce the circuit size and improve its performance. Finally, the coupling between adjacent FGC transmission lines is lower than the coupling between CPW lines for the same spacing between the lines. All of these attributes of FGC are presented in this paper.

Ponchak, George E.↗
NASA NTRS1968

Amplifier improvement circuit

Stable input stage was designed for the use with a integrated circuit operational amplifier to provide improved performance as an instrumentation-type amplifier. The circuit provides high input impedance, stable gain, good common mode rejection, very low drift, and low output impedance.

Sturman, J.↗
NASA NTRS1998

Integrated Power and Attitude Control System (IPACS)

Recent advances in materials, circuit integration and power switching have given the concept of dynamic energy and momentum storage important weight size, and operational advantages over the conventional momentum wheel-battery configuration. Simultaneous momentum and energy storage for a three axes stabilized spacecraft can be accomplished with a topology of at least four wheels where energy (a scalar) is stored or retrieved in such a manner as to keep the momentum vector invariant. This study, instead, considers the case of two counter-rotating wheels in one axis to more effectively portray the principles involved. General scalable system design equations are derived which demonstrate the role of momentum storage when combined with energy storage.

Michaelis, Theodore D.↗