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At least 649 records · Page 36
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 ~512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

Shu, Peter↗
NASA NTRS1984

Optical Testing of Integrated Circuits

Optical spot-raster scanner produces weighted photoresponse image (PI) of operating CMOS IC. Digital analysis of PI's, which correlates differences in PI's with electrical behavior of IC, shows promise both as 100-percent screening method for use in IC manufacture and as diagnostic tool in IC development.

Erickson, J.↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗
NASA NTRS1989

A digitally controlled system for effecting and presenting a selected electrical resistance

A digitally controlled resistance generator is described, in which resistors having values selected according to an expression 2(sup N-1)(R), where N is equal to the number of terms in the expression, and R is equal to the lowest value of resistance, are electrically inserted into a resistive circuit in accordance with a parallel binary signal provided by an analog-to-digital converter or a programmable computer. This binary signal is coupled via optical isolators which, when activated by a logical 1, provides a negative potential to some or all of the gate inputs of the normally on field effect transistors which, when on, shorts out the associated resistor. This applied negative potential turns the field effect transistors off and electrically inserts the resistor coupled between the source terminal and the drain terminal of that field effect transistor into the resistive circuit between the terminals.

Fletcher, James C.↗
DOE OSTI2023

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2007

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

Leon-Salas, Walter D.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS1994

Multi-speed multi-phase resolver converter

A multiphase converter circuit generates a plurality of sinusoidal outputs of displaced phase and given speed value from the output of an angular resolver system attachable to a motor excited by these multi-phase outputs, the resolver system having a lower speed value than that of the motor. The angular resolver system provides in parallel format sequential digital numbers indicative of the amount of rotation of the shaft of an angular position sensor associated with the angular resolver system. These numbers are used to excite simultaneously identical addresses of a plurality of addressable memory systems, each memory system having stored therein at sequential addresses sequential values of a sinusoidal wavetrain of a given number of sinusoids. The stored wavetrain values represent sinusoids displaced from each other in phase according to the number of output phases desired. A digital-to-analog converter associated with each memory system converts each accessed word to a corresponding analog value to generate attendant to rotation of the angular resolver a sinusoidal wave of proper phase at each of the plurality of outputs. By properly orienting the angular resolver system with respect to the rotor of the motor, essentially ripple-free torque is supplied to the rotor. The angular resolver system may employ an analog resolver feeding an integrated circuit resolver-to-digital converter to produce the requisite digital values serving as addresses. Alternative versions employing incremental or absolute encoders are also described.

Alhorn, Dean↗
NASA NTRS1995

Multi-speed multi-phase resolver converter

A multiphase converter circuit generates a plurality of sinusoidal outputs of displaced phase and given speed value from the output of an angular resolver system attachable to a motor excited by these multi-phase outputs, the resolver system having a lower speed value than that of the motor. The angular resolver system provides in parallel format sequential digital numbers indicative of the amount of rotation of the shaft of an angular position sensor associated with the angular resolver system. These numbers are used to excite simultaneously identical addresses of a plurality of addressable memory systems, each memory system having stored therein at sequential addresses sequential values of a sinusoidal wavetrain of a given number of sinusoids. The stored wavetrain values represent sinusoids displaced from each other in phase according to the number of output phases desired. A digital-to-analog converter associated with each memory system converts each accessed word to a corresponding analog value to generate attendant to rotation of the angular resolver a sinusoidal wave of proper phase at each of the plurality of outputs. By properly orienting the angular resolver system with respect to the rotor of the motor, essentially ripple-free torque is supplied to the rotor. The angular resolver system may employ an analog resolver feeding an integrated circuit resolver-to-digital converter to produce the requisite digital values serving as addresses. Alternative versions employing incremental or absolute encoders are also described.

Alhorn, Dean C.↗
NASA NTRS1985

Method and apparatus for transfer function simulator for testing complex systems

A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.

Kavaya, M. J.↗
NASA NTRS2007

Flight Qualified Micro Sun Sensor

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Liebe, Carl Christian↗
DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1996

Interface Circuit For Connecting Instruments To Computers

Circuit card designed to act as interface between K-bus remote terminal. Enables digital communication between electronic instrumentation designed to communicate with other equipment via K-bus and control and telemetry-monitoring computer designed to communicate with other equipment via MIL-STD-1553B (or MIL-STD-1773) bus. Provides K-bus interface for as many as four instrumentation circuit cards.

Katz, Richard B.↗
DOE OSTI2024

Embedded Fluidic Sensing and Control with Soft Open‐Cell Foams

Abstract The synthesis of soft matter intelligence with circuit‐driven logic has enabled a new class of robots that perform complex tasks or conform to specialized form factors in unique ways that cannot be realized through conventional designs. Translating this hybrid approach to fluidic systems, the present work addresses the need for sheet‐based circuit materials by leveraging the innate porosity of foam—a soft material—to develop pneumatic components that support digital logic, mixed‐signal control, and analog force sensing in wearables and soft robots. Analytical tools and experimental techniques developed in this work serve to elucidate compressible gas flow through porous sheets, and to inform the design of centimeter‐sized foam resistors with fluidic resistances on the order of 10 9 Pa s m −3 . When embedded inside soft robots and wearables, these resistors facilitate diverse functionalities spanning both sensing and control domains, including digital logic using textile logic gates, digital‐to‐analog signal conversion using ladder networks, and analog sensing of forces up to 40 N via compression‐induced changes in resistance. By combining features of both circuit‐based and materials‐based approaches, foam‐enabled fluidic circuits serve as a useful paradigm for future hybrid robotic architectures that fully embody the sensing and computing capabilities of soft fluidic materials.

Rajappan, Anoop↗
DOE OSTI2025

Explicit block encodings of boundary value problems for many-body elliptic operators

Simulation of physical systems is one of the most promising use cases of future digital quantum computers. In this work we systematically analyze the quantum circuit complexities of block encoding the discretized elliptic operators that arise extensively in numerical simulations for partial differential equations, including high-dimensional instances for many-body simulations. When restricted to rectangular domains with separable boundary conditions, we provide explicit circuits to block encode the many-body Laplacian with separable periodic, Dirichlet, Neumann, and Robin boundary conditions, using standard discretization techniques from low-order finite difference methods. To obtain high-precision, we introduce a scheme based on periodic extensions to solve Dirichlet and Neumann boundary value problems using a high-order finite difference method, with only a constant increase in total circuit depth and subnormalization factor. We then present a scheme to implement block encodings of differential operators acting on more arbitrary domains, inspired by Cartesian immersed boundary methods. We then block encode the many-body convective operator, which describes interacting particles experiencing a force generated by a pair-wise potential given as an inverse power law of the interparticle distance. This work provides concrete recipes that are readily translated into quantum circuits, with depth logarithmic in the total Hilbert space dimension, that block encode operators arising broadly in applications involving the quantum simulation of quantum and classical many-body mechanics.

Kharazi, Tyler [University of California, Berkeley↗
NASA NTRS1967

Electronic frequency discriminator

Digital comparator permits discrimination at accuracy of reference frequency. The compare circuit is a shift register element.

Reid, W. J.↗
NASA NTRS1971

Pneumatic oscillator Patent

Development and characteristics of fluid oscillator analog to digital converter with variable frequency controlled by signal passing through conditioning circuit

Dustin, M. O.↗