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The basic principles for qualifying silicon wafering methods are summarized, and unconventional methods of wafering was discussed. Methods of cleaving analogous to diamond cutting, geological processes employing the expansion of freezing water, and karate chops are touched upon.
Efficiency of silicon solar cells containing about one quadrillon atoms cu cm of chromium is improved about 26% by thermal annealing of the silicon wafer at a temperature of 200 C to form chromium precipitates having a diameter of less than 1 Angstrom. Further improvement in efficiency is achieved by scribing laser lines onto the back surface of the wafer at a spacing of at least 0.5 mm and at a depth of less than 13 micrometers to preferentially precipitate chromium near the back surface and away from the junction region of the device. This provides an economical way to improve the deleterious effects of chromium, one of the impurities present in metallurgical grade silicon mateial.
Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.
Slicing of silicon ingots using diamond impregnated internal diameter blade saws has been a standard technology of the semiconductor industry. This paper describes work on improvements to this technology for 10 cm diameter ingot slicing. Ingot rotation, dynamic blade edge control with feedback, mechanized blade dressing and development of thinner blades are the approaches tried. A comparison of the results for wafering with and without ingot rotation is also made. A sensitivity analysis of the major cost elements in wafering is performed for 10 cm diameter ingot and extended to the 15 cm diameter ingot case. Various parameter values such as machine cost, feed rate and consumable materials cost are identified both for single and multiple ingot slicing.
Improved switching transistors handle 400-A peak currents and up to 1,200 V. Using large diameter silicon wafers with twice effective area as D60T, form basis for D7 family of power switching transistors. Package includes npn wafer, emitter preform, and base-contact insert. Applications are: 25to 50-kilowatt high-frequency dc/dc inverters, VSCF converters, and motor controllers for electrical vehicles.
Lead chalcogenide photoresistors integrated with FET amplifiers. Circuit combines voltage divider containing lead chalcogenide photoresistor with FET source follower. Source and drain of FET p-doped regions in underlying n-type silicon wafer. All other structures formed at or deposited above original surface plane of wafer.
A new innovative planar multijunction solar cell chip for concentrated sunlight applications is proposed. The chip consists of many voltage-generating regions, called unit cells, which are connected in series within a single silicon wafer, thereby providing a high open-circuit voltage at multiple sun illumination levels. The unit cells are fabricated on 75 micron thick p-type single crystal silicon substrate. Each chip consists of 1.42 x 9.63 mm n(+)/p collecting junctions on the back of the wafer, while the illuminated front surface area is divided into 0.3 micron deep n(+) regions. The fabrication sequence includes standard degreasing and cleaning procedures, double-sided alignment photomasking, introduction of boron and phosphorus impurities, and photolithography. The open circuit voltage of the chip increased rapidly with illumination up to about 4 AM1 suns, and then began to saturate at the sum of the individual unit cell voltages of 3.5 above 4 AM1 suns. A short circuit density per unit cell of 300 mA/sq cm at 20 AM1 suns was observed.
Thin buffer layer of SiC minimizes effects of lattice mismatch. Approach consists of growing single-crystal layer of cubic SiC on single-crystal silicon (Si) wafer by chemical-vapor deposition (CVD). Process developed for production of large-area single-crystal wafers of cubic silicon carbide (SiC) for semiconductor devices; also used to make devices themselves. Applications include electronics for high temperature (up to 900 C) and electronics for very high frequencies.
The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.
An X-ray spectrometer for providing imaging and energy resolution of an X-ray source is described. This spectrometer is comprised of a thick silicon wafer having an embedded matrix or grid of aluminum completely through the wafer fabricated, for example, by thermal migration. The aluminum matrix defines the walls of a rectangular array of silicon X-ray detector cells or pixels. A thermally diffused aluminum electrode is also formed centrally through each of the silicon cells with biasing means being connected to the aluminum cell walls and causes lateral charge carrier depletion between the cell walls so that incident X-ray energy causes a photoelectric reaction within the silicon producing collectible charge carriers in the form of electrons which are collected and used for imaging.
Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.
Attachment for reciprocating power-saw maintains nearly constant cutting pressure even though kerf length varies. Attachment developed for wire saws used to slice cylindrical silicon ingots into wafers for semiconductor devices. By maintaining constant pressure, attachment helps to ensure smooth, flat, uniform wafers. Principle adaptable to straight, toothed saws as well as to wire saws.
The objective of this program is to develop 60 GHz GaAs IMPATT Diodes suitable for communications applications. The performance goal of the 60 GHz IMPATT is 1W CW output power with a conversion efficiency of 15 percent and 10 year life time. During the course of the program, double drift (DD) GaAs IMPATT Diodes have been developed resulting in the state of the art performance at V band frequencies. A CW output power of 1.12 W was demonstrated at 51.9 GHz with 9.7 percent efficiency. The best conversion efficiency achieved was 15.3 percent. V band DD GaAs IMPATTs were developed using both small signal and large signal analyses. GaAs wafers of DD flat, DD hybrid, and DD Read profiles using molecular beam epitaxy (MBE) were developed with excellent doping profile control. Wafer evaluation was routinely made by the capacitance versus voltage (C-V) measurement. Ion mass spectrometry (SIMS) analysis was also used for more detailed profile evaluation.
Although GaAs solar cells are radiation-resistant and have high conversion efficiencies, there are two major obstacles that such cells must overcome before they can be widely adopted for space applications: GaAs wafers are too expensive and cells made from these wafers are too heavy. The CLEFT process permits the growth of thin single-crystal films on reusable substrates, resulting in a drastic reduction in both cell cost and cell weight. Recent advances in CLEFT technology have made it possible to achieve efficiencies of about 14 percent AM0 for 0.51-sq cm GaAs solar cells 5 microns thick with a 41-mil-thick coverglass. In preliminary experiments efficiencies close to 19 percent AM1 have been obtained for 10-micron-thick cells. It is suggested that the CLEFT technology should yield inexpensive, highly efficient modules with a beginning-of-life specific power close to 1 kW/kg (for a coverglass thickness of 4 mils).
An experiment to investigate the spatial homogeneity of large-grain polycrystalline silicon shows a number of performance-loss mechanisms. Arrays of up to 400 small (about 0.2 sq cm in area) photodiodes were fabricated on a selection of 10 cm x 10 cm polycrystalline silicon wafers. Measurements of the illuminated current-voltage (J-V) characteristics were used to generate maps of Voc, Jsc, and FF as a function of position; and dark J-V and LBIC analysis were used to determine the cause of low performance in areas with significantly degraded J-V characteristics. In addition to the presence of inclusions, which act as resistive shunts, the performance of many of the cells is limited by quasineutral recombination current, which may vary by up to an order of magnitude across a wafer. The increase is the result of either electrically-active grain boundaries or numerous subgrain boundaries within the grain bulk. In other isolated instances, the open-circuit voltage is reduced by excess space-charge recombination current that is not correlated with either grain or subgrain boundary activity.
Fracture mechanics test methods are applied to evaluate the proof test characteristics of silicon Cz wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof testing and no subcritical crack growth in silicon is observed during proof loading. Mechanical proof testing appears to be an effective method to eliminate weak samples before cell processing.
X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.
Microscopic circuit structures prepared for probing. Xenon difluoride removes relatively large amounts of silicon from integratedcircuit or solar-cell structures while leaving SiO2, Si3N4, Al2O3, and other compounds intact. In Etching Apparatus, solid XeF2 sublimated in vacuum, then allowed to flow over sample at controlled rate and pressure. Wafer etched from back to expose SiO2 and Al layers for spectroscopic analysis of SiO2/Al interface. Using XeF2 technique, silicon wafer with oxide layer reduced in thickness from standard 300 micrometer to as little as 10 nanometer without adversely affecting oxide.