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Technique can provide four-phase clock signal from single-phase clock and requires only one power supply voltage. This arrangement saves considerable power compared to circuits having load resistor between power supply and ground.
Detector consists of matrix of storage elements which are activated by coincidence of failure-voltage pulses and clock pulses. Clock frequency used for event sequence detector can be selected to provide time resolution demanded by test at hand.
Synchronous phase-lock-loop detector accepts distorted input and generates jitter-free clock. Data-detection circuitry takes advantage of this clock and employs integrate-and-dump decision circuit to provide near-theoretically ideal data decoding.
After amplification and normalization, incoming data bits are fed, alternately, to pair of integrators. While one integrator is operating, content of other is on hold, sample, and dump. Clock derived in bit-timing extractor times and controls integrators. Frequency of clock is one-half data rate.
An event sequence detector is described with input units, each associated with a row of bistable elements arranged in an array of rows and columns. The detector also includes a shift register which is responsive to clock pulses from any of the units to sequentially provide signals on its output lines each of which is connected to the bistable elements in a corresponding column. When the event-indicating signal is received by an input unit it provides a clock pulse to the shift register to provide the signal on one of its output lines. The input unit also enables all its bistable elements so that the particular element in the column supplied with the signal from the register is driven to an event-indicating state.
Perform analog-to-digital conversion on input signal with staircase circuit having 10% resolution, convert digital result to analog voltage, subtract it from original input signal; read out feedback signals as decimal digit representation during one clock phase and servo-error difference between input and feedback as analog portion during following clock phase.
Solutions are provided to specific problems arising in the GSFC VHF-PSK and VHF-FSK Command Systems in support of establishment and maintenance of Data Systems Standards. Signal structures which incorporate transmission on the uplink of a clock along with the PSK or FSK data are considered. Strategies are developed for allocating power between the clock and data, and spectral analyses are performed. Bit error probability and other probabilities pertinent to correct transmission of command messages are calculated. Biphase PCM/PM and PCM/FM are considered as candidate modulation techniques on the telemetry downlink, with application to command verification. Comparative performance of PCM/PM and PSK systems is given special attention, including implementation considerations. Gain in bit error performance due to coding is also considered.
The effects of the Refan JT8D side engine target thrust reverser on the stability and control characteristics of the Boeing 727-200 airplane were investigated using the Boeing-Vertol 20 x 20 ft Low-Speed Wind Tunnel. A powered model of the 727-200 was tested in groud effect in the landing configuration. The Refan target reverser configuration was evaluated relative to the basic production 727 airplane with its clamshell-deflector door thrust reverser design. The Refan configuration had slightly improved directional control characteristics relative to the basic airplane. Clocking the Refan thrust reversers 20 degrees outboard to direct the reverser flow away from the vertical tail, had little effect on directional control. However, clocking them 20 degrees inboard resulted in a complete loss of rudder effectiveness for speeds greater than 90 knots. Variations in Refan reverser lip/fence geometry had a minor effect on directional control.
A report is presented of the results observed in comparison between LORAN-C and accurate portable clocks carried to the stations of NASA's world-wide space tracking and data network. It is believed that such information can provide a meaningful determination of the accuracy of the LORAN-C technique. The investigation shows the need for the employment of portable clocks during, or shortly after the installation of LORAN-C receivers.
Simplified binary-data transition detector, for synchronization of relatively noise-free signals, can be used with radio or cable data-control links. It permits reception of binary data in absence of clock signal or self-clocking coder.
Starting with an assumed ideal network having perfect clocks at every node and known fixed transmission delays between nodes, the effects of adding tolerances to both transmission delays and nodal clocks is described. The advantages of controlling tolerances on time rather than frequency are discussed. Then a concept is presented for maintaining these tolerances on time throughout the network. This concept, called time reference distribution, is a systematic technique for distributing time reference to all nodes of the network. It is reliable, survivable and possesses many other desirable characteristics. Some of its features such as an excellent self monitoring capability will be pointed out. Some preliminary estimates of the accuracy that might be expected are developed and there is a brief discussion of the impact upon communication system costs. Time reference distribution is a concept that appears very attractive. It has not had experimental evaluation and has not yet been endorsed for use in any communication network.
The Defense Communication System will be moving rapidly toward providing switched digital service to it's users within the next ten years. The principal driving force in the transition to a digital system is the requirement for high performance secure voice service. Additionally, the anticipated data requirements in this time frame can be handled most effectively by a digital network. The characteristics of a switched digital network which impose timing and synchronization requirements on the system design are presented. Several alternative approaches to implementing a timing subsystem suitable for a switched digital communications system have been considered. These include pulse stuffing, independent stable clocks, and clock correction techniques. The advantages and disadvantages of each approach are discussed relative to both the strategic and tactical communication system requirements.
A system capable of generating every possible data frame subperiod and delayed subperiod of a data frame of length of M clock pulse intervals (CPIs) comprised of parallel modulo-m sub i counters is presented. Each m sub i is a prime power divisor of M and a cascade of alpha sub i identical modulo-p sub i counters. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. Every possible nontrivial data frame subperiod and delayed subperiod is derived and a specific CPI in the data frame is detected. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.
The methods of synchronizing precision clocks will be reviewed placing particular attention to the simpler techniques, their accuracies, and the approximate cost of equipment. The more exotic methods of synchronization are discussed in lesser detail. The synchronization techniques that will be covered will include satellite dissemination, communication and navigation transmissions via VLF, LF, HF, UHF and microwave as well as commercial and armed forces television. Portable clock trips will also be discussed.
The accuracy of geodetic and astrometric information obtained from very long baseline interferometry (VLBI) observations is dependent upon the stability of the frequency standard, or clock, used at each site of VLBI array. The sensitivities of two hydrogen maser frequency standards of different design to pressure, temperature, and magnetic field variations were measured; and, for one of the standards, sensitivity was found to be severe enough to degrade the information content of VLBI measurements. However, the effect on the geometric and astrometric information of such clock instabilities, with time scales of hours or greater, can be sharply reduced through the use of differencing techniques.
Accurate baseline determinations and clock synchronization results obtained from the Quasar Patrol observations at X band with the Goldstone-Haystack baseline are presented. In addition, data from stations at Greenbank, West Virginia, and Onsala, Sweden were used. It was estimated that clock accuracy was on the order of 16 cm.
The relativistic conversion between coordinate time and atomic time is reformulated to allow simpler time calculations relating analysis in solar system barycentric coordinates (using coordinate time) with earth-fixed observations (measuring 'earth-bound' proper time or atomic time). After an interpretation in terms of relatively well-known concepts, this simplified formulation, which has a rate accuracy of about 10 to the minus 15th, is used to explain the conventions required in the synchronization of a worldwide clock network and to analyze two synchronization techniques - portable clocks and radio interferometry. Finally, pertinent experimental tests of relativity are briefly discussed in terms of the reformulated time conversion.
An interface logic circuit permitting the transfer of information between two computers having asynchronous clocks is disclosed. The information transfer involves utilization of control signals (including request, return-response, ready) to generate properly timed data strobe signals. Noise problems are avoided because each control signal, upon receipt, is verified by at least two clock pulses at the receiving computer. If control signals are verified, a data strobe pulse is generated to accomplish a data transfer. Once initiated, the data strobe signal is properly completed independently of signal disturbances in the control signal initiating the data strobe signal. Completion of the data strobe signal is announced by automatic turn-off of a return-response control signal.