System for generating timing and control signals

Abstract

A system capable of generating every possible data frame subperiod and delayed subperiod of a data frame of length of M clock pulse intervals (CPIs) comprised of parallel modulo-m sub i counters is presented. Each m sub i is a prime power divisor of M and a cascade of alpha sub i identical modulo-p sub i counters. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. Every possible nontrivial data frame subperiod and delayed subperiod is derived and a specific CPI in the data frame is detected. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.