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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 613 records · Page 34
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Automatic gain control

An automatic gain control (AGC), designed to operate with the prototype Loran-C receiver, is described. The device is used to eliminate error which occurs when signals are received at different magnitudes. The automatic gain control is a three transistor circuit which requires a constant dc voltage of 8 volts. Tests conclude that this value may be in the range of 4 to 12 v without change in circuit performance. Two transistors are cascaded to pass and amplify the input signal. Their gain is controlled by a third transistor which itself is controlled by an external AGC voltage between 0 and 8 volts dc. The integrated circuit used is an 8 pin chip, which is a differential cascade amplifier designed for use in communications operating at frequencies from dc to 120 MHz. The integrated circuit was balanced for AGC capabilities, and has a wide operating current range. The maximum input current at pins 1 and 5 is 0.1 mAmps. AGC testing is described.

Roman, J. P.↗
DOE OSTI2022

Packet router with virtual channel hop buffer control

An integrated circuit includes a network on chip (NOC) that includes a plurality of processing elements and a plurality of NOC nodes, interconnected to the plurality of processing elements. The integrated circuit includes logic that is configured to: increment by one, a virtual channel identifier to produce an incremented destination VC identifier, the virtual channel (VC) identifier associated with at least portion of a packet stored in at least one virtual channel buffer; determine that a destination virtual channel buffer corresponding to the incremented destination VC identifier in a destination NOC node in the NOC is available to store the portion of the packet; and in response to the determination, send the portion of the packet and the incremented destination VC identifier to the destination NOC node.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1989

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗
NASA NTRS1979

Feasibility study of silicon nitride protection of plastic encapsulated semiconductors

The application of low temperature silicon nitride protective layers on wire bonded integrated circuits mounted on lead frame assemblies is reported. An evaluation of the mechanical and electrical compatibility of both plasma nitride and photochemical silicon nitride (photonitride) passivations (parallel evaluations) of integrated circuits which were then encapsulated in plastic is described. Photonitride passivation is compatible with all wire bonded lead frame assemblies, with or without initial chip passivation. Plasma nitride passivation of lead frame assemblies is possible only if the chip is passivated before lead frame assembly. The survival rate after the environmental test sequence of devices with a coating of plasma nitride on the chip and a coating of either plasma nitride or photonitride over the assembled device is significantly greater than that of devices assembled with no nitride protective coating over either chip or lead frame.

Peters, J. W.↗
DOE OSTI2023

Piezoelectric deformable photonic devices

A CMOS-compatible actuator platform for implementing phase, amplitude, and frequency modulation in silicon nitride photonic integrated circuits via piezo-optomechanical coupling using tightly mechanically coupled aluminum nitride actuators is disclosed. The platform, which may be fabricated in a CMOS foundry, enables scalable active photonic integrated circuits for visible wavelengths, and the piezoelectric actuation functions without performance degradation down to cryogenic operating temperatures. A number of devices are possible, including ring modulator devices, phase shifter devices, Mach-Zehnder interferometer devices, directional coupler devices (including tunable directional coupler devices), and acousto-optic modulator and frequency shifter devices, each of which can employ the same AlN actuator platform. As all of these devices can be built on the same AlN actuator platform, numerous optical functions can be implemented on a single die.

Eichenfield, Matt↗
DOE OSTI2020

Novel spectral-shaping building block: a narrowband Mach–Zehnder interferometer

We present an experimental demonstration of notch filters with arbitrary center wavelengths capable of tunable analog output power values varying between full extinction of 15 and 0 dB. Each filter is composed of highly modular apodized four-port Bragg add/drop filters to reduce the crosstalk between concatenated devices. The constructed photonic integrated circuit experimentally demonstrates spectra shaping using four independent notch filters. Each notch filter supports a bandwidth of ∼ 2 nm and is shown to be suitable for realization of programmable photonic integrated circuits.

Davis, Jordan A. (ORCID:0000000343483295)↗
NASA NTRS1993

A low-mass faraday cup experiment for the solar wind

Faraday cups have proven to be very reliable and accurate instruments capable of making 3-D velocity distribution measurements on spinning or 3-axis stabilized spacecraft. Faraday cup instrumentation continues to be appropriate for heliospheric missions. As an example, the reductions in mass possible relative to the solar wind detection system about to be flown on the WIND spacecraft were estimated. Through the use of technology developed or used at the MIT Center for Space Research but were not able to utilize for WIND: surface-mount packaging, field-programmable gate arrays, an optically-switched high voltage supply, and an integrated-circuit power converter, it was estimated that the mass of the Faraday Cup system could be reduced from 5 kg to 1.8 kg. Further redesign of the electronics incorporating hybrid integrated circuits as well as a decrease in the sensor size, with a corresponding increase in measurement cycle time, could lead to a significantly lower mass for other mission applications. Reduction in mass of the entire spacecraft-experiment system is critically dependent on early and continual collaborative efforts between the spacecraft engineers and the experimenters. Those efforts concern a range of issues from spacecraft structure to data systems to the spacecraft power voltage levels. Requirements for flight qualification affect use of newer, lighter electronics packaging and its implementation; the issue of quality assurance needs to be specifically addressed. Lower cost and reduced mass can best be achieved through the efforts of a relatively small group dedicated to the success of the mission. Such a group needs a fixed budget and greater control over quality assurance requirements, together with a reasonable oversight mechanism.

Lazarus, A. J.↗
NASA NTRS2005

Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction

Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.

Ngo, Quoc↗
DOE OSTI2020

Wavefront detector

A wavefront sensor system suitable for integration into an integrated circuit light detector may provide for wave angle sensors having varying functional relationships between the wave angle and signal to provide improved dynamic range. These wave angle sensors may be combined with integrated circuit phase angle sensors for a more complete analysis of the waveform.

42 ENGINEERING↗
DOE OSTI2021

Wavefront detector

A wavefront sensor system suitable for integration into an integrated circuit light detector may provide for wave angle sensors having varying functional relationships between the wave angle and signal to provide improved dynamic range. These wave angle sensors may be combined with integrated circuit phase angle sensors for a more complete analysis of the waveform.

Yu, Zongfu↗
NASA NTRS1985

Onboard high data rate signal processing and storage

The objective is to advance the state of the art in onboard image data processing and storage through the use of advanced gallium arsenide integrated circuit technology. Viewgraphs are given on research and development efforts, an adaptive programmable processor chip set, design characteristics of an eight bit general processor, and a density comparison of silicon and gallium arsenide integrated circuits.

Miller, Warner H.↗
NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗
NASA NTRS1981

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.↗
NASA NTRS1986

Multifunction Vacuum Chamber for IC Metallization

Vacuum system chamber processing multilayer metallization on integrated circuits (IC's) performs four operations ordinarily done in separated equipment. Chamber etches holes, removes photoresist, cleans by sputter etching, and deposits final layer of metal. Combinedfunction chamber costs less than separate equipment. Chamber avoids exposing integrated circuits to room air and, to oxidation and dust, between steps. Eliminates time spent in transferring circuits from one apparatus to next.

Routh, D. E.↗
NASA NTRS1992

Responses Of A DRAM To Energetic Heavy Ions

Report presents results of experiments where multiple-bit errors were induced in 256-kbit commercial integrated-circuit dynamic random-access memory (DRAM) by variety of normally incident heavy ions. Idea demonstrates utility of DRAM and methods used to analyze experimental data, with view towards applying methods and data to other digital integrated circuits.

Zoutendyk, John A.↗
NASA NTRS2007

Advanced High-Definition Video Cameras

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Glenn, William↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗