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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

Architectural Techniques For Managing Non-volatile Caches

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making them a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.

Cache architecture↗
DOE OSTI2013

A Survey of Architectural Techniques For Improving Cache Power Efficiency

Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-world processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling low-power operation of caches.

architectural techniques↗
DOE OSTI2014

Multiprocessor switch with selective pairing

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

Computing an operating parameter of a unified power flow controller

A Unified Power Flow Controller described herein comprises a sensor that outputs at least one sensed condition, a processor that receives the at least one sensed condition, a memory that comprises control logic that is executable by the processor; and power electronics that comprise power storage, wherein the processor causes the power electronics to selectively cause the power storage to act as one of a power generator or a load based at least in part upon the at least one sensed condition output by the sensor and the control logic, and wherein at least one operating parameter of the power electronics is designed to facilitate maximal transmittal of electrical power generated at a variable power generation system to a grid system while meeting power constraints set forth by the electrical power grid.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

System-wide power management control via clock distribution network

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2014

Optimization and Parallelization of the Thermal-Hydraulic Sub-channel Code CTF for High-Fidelity Multi-physics Applications

This paper describes major improvements to the computational infrastructure of the CTF sub-channel code so that full-core sub-channel-resolved simulations can now be performed in much shorter run-times, either in stand-alone mode or as part of coupled-code multi-physics calculations. These improvements support the goals of the Department Of Energy (DOE) Consortium for Advanced Simulations of Light Water (CASL) Energy Innovation Hub to develop high fidelity multi-physics simulation tools for nuclear energy design and analysis. A set of serial code optimizations--including fixing computational inefficiencies, optimizing the numerical approach, and making smarter data storage choices--are first described and shown to reduce both execution time and memory usage by about a factor of ten. Next, a Single Program Multiple Data (SPMD) parallelization strategy targeting distributed memory Multiple Instruction Multiple Data (MIMD) platforms and utilizing domain-decomposition is presented. In this approach, data communication between processors is accomplished by inserting standard MPI calls at strategic points in the code. The domain decomposition approach implemented assigns one MPI process to each fuel assembly, with each domain being represented by its own CTF input file. The creation of CTF input files, both for serial and parallel runs, is also fully automated through use of a pre-processor utility that takes a greatly reduced set of user input over the traditional CTF input file. To run CTF in parallel, two additional libraries are currently needed; MPI, for inter-processor message passing, and the Parallel Extensible Toolkit for Scientific Computation (PETSc), which is leveraged to solve the global pressure matrix in parallel. Results presented include a set of testing and verification calculations and performance tests assessing parallel scaling characteristics up to a full core, sub-channel-resolved model of Watts Bar Unit 1 under hot full-power conditions (193 17x17 assemblies, ~56,000 pins, ~59,000 sub-channels, ~2.8 million thermal-hydraulic (TH) control volumes). Results demonstrate that CTF can now perform full core analysis (not previously possible due to excessively long runtimes and memory requirements) on the order of 20 minutes. This new capability is not only useful to standalone CTF users, but is also being leveraged in support of coupled code multi-physics calculations being done in the CASL program.

COBRA-TF↗
DOE OSTI2014

Domi

Domi (Greek for "structure") is a Trilinos package that provides support for multi-dimensional data arrays distributed over multiple processors of a high performance computing system. The software supports data arrays of arbitrary number of dimensions mapped to a multi-dimensional grid of processors. Domi provides local access to the data, as well as the ability to compute global quantities such as norms, maxima and minima. Data arrays can be constructed with boundary and communication padding, necessary for finite difference algorithms, and provides high-level methods for communicating data between processors to update these buffers. The distributed maps and vectors in Domi can be converted to the equivalent data structures in Epetra and Tpetra (both of which assume unstructured data), using view semantics when appropriate, for use with other Trilinos solvers.

Spotz, William F.↗
DOE OSTI2016

Single bus star connected reluctance drive and method

A system and methods for operating a switched reluctance machine includes a controller, an inverter connected to the controller and to the switched reluctance machine, a hysteresis control connected to the controller and to the inverter, a set of sensors connected to the switched reluctance machine and to the controller, the switched reluctance machine further including a set of phases the controller further comprising a processor and a memory connected to the processor, wherein the processor programmed to execute a control process and a generation process.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2016

System and method for memory allocation in a multiclass memory system

A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Active non-volatile memory post-processing

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

System on chip module configured for event-driven architecture

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Computing an operating parameter of a unified power flow controller

A Unified Power Flow Controller described herein comprises a sensor that outputs at least one sensed condition, a processor that receives the at least one sensed condition, a memory that comprises control logic that is executable by the processor; and power electronics that comprise power storage, wherein the processor causes the power electronics to selectively cause the power storage to act as one of a power generator or a load based at least in part upon the at least one sensed condition output by the sensor and the control logic, and wherein at least one operating parameter of the power electronics is designed to facilitate maximal transmittal of electrical power generated at a variable power generation system to a grid system while meeting power constraints set forth by the electrical power grid.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2018

Near-memory data reorganization engine

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine ("DRE"). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Producing EGS4 Shower Displays with the Unified Graphics System

The EGS4 Code System has been coupled with the SLAC Unified Graphics System in such a manner as to provide a means for displaying showers on UGS77-supported devices. This is most easily accomplished by attaching an auxiliary subprogram package (SHOWGRAF) t o existing EGS4 User Codes and making use of a graphics display or a post-processor code called EGS4PL. SHOWGRAF shower displays directly on interactive ing three-dimensional rotations, translations, may be used to create IBM 5080 color display devices, support- and zoom features, and providing illustration of particle types and energies by color and/or intensity. Alternatively, SHOWGRAF may be used to record a two-dimensional projection of the shower in a device-independent graphics file. The EGS4PL post-processor may then be used to convert this file into device-dependent graphics code for any UGS77-supported device. Options exist within EGS4PL that allow for two-dimensional translations and zoom, for creating line structure to indicate particle types and energies, and for optional display of particles by type. All of this is facilitated by means of the command processor EGS4PL EXEC together with new options (5080 and PDEV) with the standard EGS4IN EXEC routine for running EGS4 interactively under VM/SP.

Cowan, R.↗
DOE OSTI2018

Hardware accuracy counters for application precision and quality feedback

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

Apparatus, system, and method for sensor authentication

A method includes receiving an output signal from a sensor, recovering a noise signal from the output signal, comparing the noise signal with a stored baseline noise signature, and reporting authentication of the sensor if the comparison is within a pre-determined error limit. A sensor authentication apparatus, comprises a processor and a memory operably coupled with the processor. Instructions, when executed, cause the processor to separate a noise signal from a measured signal, and detect a noise signature match by comparing the noise signal with at least one stored baseline noise signature associated with the sensor. A sensor authentication system comprises a sensor authentication unit and a data acquisition unit. At least one of the sensor authentication unit and the data acquisition unit is configured to compare a noise signal with a baseline noise signature to authenticate the at least one sensor from among a plurality of sensors.

Svoboda, John M.↗
DOE OSTI2018

System on chip module configured for event-driven architecture

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

System and method for groundwater detection and evaluation

A system for mapping a depth of an aquifer and determining the presence and salinity of water from the aquifer and methods for using the making/using the same includes a central processor. One or more horizontal loop transmitters can be coupled to the central processor, wherein said one or more horizontal loop transmitters produce a first half-sine pulse of magnetic field at a first pulse duration for measuring the resistivity of a ground surface. The one or more horizontal loop transmitters can produce a second sequence of half-sine pulses at a second frequency for creating an excitation field for magnetic resonance sounding. A multi-turn receiver loop antenna can also be coupled to the central processor, wherein said multi-turn receiver loop antenna receives an induced magnetic field from said one or more horizontal loop transmitters that is representative of the depth of an aquifer and the salinity of the water.

47 OTHER INSTRUMENTATION↗