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DOE OSTI · 1126499

Multiprocessor switch with selective pairing

Gara, Alan·Gschwind, Michael K·Salapura, Valentina
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Abstract

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

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BibTeXRIS

Gara, Alan, Gschwind, Michael K, Salapura, Valentina. 2014-03-11. Multiprocessor switch with selective pairing. https://www.osti.gov/biblio/1126499

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