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At least 541 records · Page 30
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.↗
NASA NTRS1986

Multifunction Vacuum Chamber for IC Metallization

Vacuum system chamber processing multilayer metallization on integrated circuits (IC's) performs four operations ordinarily done in separated equipment. Chamber etches holes, removes photoresist, cleans by sputter etching, and deposits final layer of metal. Combinedfunction chamber costs less than separate equipment. Chamber avoids exposing integrated circuits to room air and, to oxidation and dust, between steps. Eliminates time spent in transferring circuits from one apparatus to next.

Routh, D. E.↗
NASA NTRS1992

Responses Of A DRAM To Energetic Heavy Ions

Report presents results of experiments where multiple-bit errors were induced in 256-kbit commercial integrated-circuit dynamic random-access memory (DRAM) by variety of normally incident heavy ions. Idea demonstrates utility of DRAM and methods used to analyze experimental data, with view towards applying methods and data to other digital integrated circuits.

Zoutendyk, John A.↗
NASA NTRS2007

Advanced High-Definition Video Cameras

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Glenn, William↗
NASA NTRS2011

High-Efficiency Ka-Band Waveguide Two-Way Asymmetric Power Combiner

NASA is planning a number of Space Exploration, Earth Observation and Space Science missions where Ka-band solid-state power amplifiers (SSPAs) could have a role. Monolithic microwave integrated circuit (MMIC) based SSPAs with output powers on the order of 10 W at Ka-band frequencies would be adequate to satisfy the data transmission rate requirements at the distances involved. MMICs are a type of integrated circuit fabricated on a GaAs wafer, which operates at micro wave frequencies and performs the function of signal amplification. The highest power Ka-band (31.8 to 32.3 GHz) SSPA to have flown in space had an output power of 2.6 W with an overall efficiency of 14.3 percent. This SSPA was built around discrete GaAs pHEMT (high electron mobility transistor) devices and flew aboard the Deep Space One spacecraft. State-of-the-art GaAs pHEMT-based MMIC power amplifiers (PAs) can deliver RF power at Ka-band frequencies anywhere from 3 W with a power added efficiency (PAE) of 32 percent to 6 W with a PAE of 26 percent. However, to achieve power levels higher than 6 W, the output of several MMIC PAs would need to be combined using a high-efficiency power combiner. Conventional binary waveguide power combiners, based on short-slot and magic-T circuits, require MMIC PAs with identical amplitude and phase characteristics for high combining efficiency. However, due to manufacturing process variations, the output powers of the MMIC PAs tend to be unequal, and hence the need to develop unequal power combiners. A two-way asymmetric magic-T based power combiner for MMIC power amplifiers, which can take in unequal inputs, has been successfully designed, fabricated, and characterized over NASA s Deep Space Network (DSN) frequency range of 31.8 to 32.3 GHz. The figure is a transparent view of the a sym - metric combiner that shows the 4-port configuration and the internal structure. The rod, post, and iris are positioned by design to achieve the desired asymmetric power ratio, phase equality, and port isolation. Although the combiner was designed for an input power ratio of 2:1, it can be custom-designed for any arbitrary power ratio and frequency range. The manufactured prototype combiner was precision machined from aluminum and is less than 2 in.3 (32.8 cm3). Previously investigated rectangular waveguide unequal power combiners were based on shunt/series coupling slots, E-plane septums, or H-plane T-junctions. All the prior art unequal power combiners operated at or below X-band (10 GHz) frequencies and were primarily used in the feed network of antenna arrays. The only reported asymmetric magic-T was developed as a 2:1 power divider for operation at a much lower frequency, around 500 MHz. The measured power ratio when tested as a power divider was very close to 2 and the phase balance was within 2.6, resulting in near ideal performance. When tested as a combiner using two MMIC SSPAs with a 2:1 power output ratio, an efficiency greater than 90 percent was demonstrated over the 500 MHz DSN frequency range. The return loss at the combiner output port (1) was greater than 18 dB and the input port (2 and 3) isolation was greater than 22 dB. The results show the asymmetric combiner to be a good candidate for high-efficiency power combining of two or more SSPAs needed to achieve the 6 to 10 W required by space communications systems of future NASA missions.

Wintucky, E. G.↗
NASA NTRS1994

Feasibility study, software design, layout and simulation of a two-dimensional Fast Fourier Transform machine for use in optical array interferometry

The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a time-domain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).

Boriakoff, Valentin↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
NASA NTRS2013

Development of a 2K x 2K GaAs QWIP Focal Plane Array

We are developing the next generation of GaAs Quantum Well Infrared Photodetector (QWIP) focal plane arrays (FPAs) in preparation for future NASA space-borne Earth observing missions. It is anticipated that these missions will require both wider ground spatial coverage as well as higher ground imaging resolution. In order to demonstrate our capability in meeting these future goals we have taken a two-tiered approach in the next stage of advanced QWIP focal plane array development. We will describe our progress in the development of a 512 x 3,200 (512 x 3K) array format for this next generation thermal imaging array for the NASA Landsat project. However, there currently is no existing readout integrated circuit (ROIC) for this format array.so to demonstrate the ability to scale-up an existing ROIC we developed a 1,920 x 2,048 (2K x 2K) array and it hybridized to a Raytheon SB419 CTIA readout integrated circuit that was scaled up from their existing 512 x 640 SB339 ROIC. Two versions of the 512 x 3K QWIP array were fabricated to accommodate a future design scale-up of both the Indigo 9803 ROIC based on a 25 micron pixel dimension and a scale up of the Indigo 9705 ROIC based on a 30 micron pixel dimension. Neither readout for the 512 x 3K has yet to be developed but we have fabricated both versions of the array. We describe the design, development and test results of this effort as well as the specific applications these FPAs are intended to address.

Jhabvala, M.↗
NASA NTRS1994

Making A D-Latch Sensitive To Alpha Particles

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Buehler, Martin G.↗
NASA NTRS2008

Prolonged 500 C Operation of 6H-SiC JFET Integrated Circuitry

This paper updates the long-term 500 C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 degC with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 C before failure.

Neudeck, Philip G.↗
NASA NTRS1999

Novel Three-Dimensional Vertical Interconnect Technology for Microwave and RF Applications

In this paper, novel 3D interconnects suitable for applications in microwave and RF integrated circuit technology have been presented. The interconnect fabrication process and design details are presented. In addition, measured and numerically modeled results of the performance of the interconnects have been shown. The results indicate that the proposed technology has tremendous potential applications in integrated circuit technology. C,

Goverdhanam, Kavita↗
NASA NTRS1976

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Mandal, R. P.↗
NASA NTRS1982

Advanced digital SAR processing study

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented.

Martinson, L. W.↗
NASA NTRS1992

Quartz/fused silica chip carriers

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Source record↗
NASA NTRS2007

VLSI Design of a Turbo Decoder

A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

Fang, Wai-Chi↗
NASA NTRS1973

On the performance of block codes

It is important to define and evaluate measures which incorporate most, if not all, of the quantities affecting the overall system reliability. For the simple types of block codes normally employed in space communication systems, the complexity of the encoder and decoder is of little consequence, since the use of integrated circuit technology allows the construction of the basic components in an inexpensive fashion. The complexity is essentially independent of the particular code-decoder used. The processing speed is generally a function of the type of logic used and the technology in the construction of the integrated circuits.

Helgert, H. J.↗
NASA NTRS2009

Alternative Packaging for Back-Illuminated Imagers

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Pain, Bedabrata↗
NASA NTRS1989

Image processing using Gallium Arsenide (GaAs) technology

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Miller, Warner H.↗