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At least 55 records · Page 3

A 90 GHz Amplifier Assembled Using a Bump-Bonded InP-Based HEMT

We report on the performance of a novel W-band amplifier fabricated utilizing very compact bump bonds. We bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) onto a separately fabricated passive circuit having a GaAs substrate. The compact bumps and small chip size were used for efficient coupling and maximum circuit design flexibility. This new quasi-monolithic millimeter-wave integrated circuit (Q-MMIC) amplifier exhibits a peak gain of 5.8 dB at approx. 90 GHz and a 3 dB bandwidth of greater than 25%. To our knowledge, this is the highest frequency amplifier assembled using bump-bonded technology. Our bump-bonding technique is a useful alternative to the high cost of monolithic millimeter-wave integrated circuits (MMIC's). Effects of the bumps on the circuit appear to be minimal. We used the simple matching circuit for demonstrating the technology - future circuits would have all of the elements (resistors, via holes, bias lines, etc.) included 'in conventional MMIC's. Our design in different from other investigators' efforts in that the bumps are only 8 microns thick by 15 microns wide. The bump sizes were sufficiently small that the devices, originally designed for W-band hybrid circuits, could be bonded without alteration. Figure 3 shows the measured and simulated magnitude of S-parameters from 85-120 GHz, of the InP HEMT bump-bonded to the low noise amplifier (LNA) passive. The maximum gain is 5.8 dB at approx. 90 GHz, and gain extends to 117 GHz. Measurement of a single device (without matching networks) shows approx. 1 dB of gain at 90 GHz. The measured gain of the amplifier agrees well with the design in the center of the measurement band, and the agreement falls off at the band edges. Since no accommodation for the bump-bonding parasitics was made in the design, the result implies that the parasitic elements associated with the bonding itself do not dominate the performance of the LNA circuit. It should be noted that this amplifier was designed for good noise performance, which is why the input and output return losses are poorer than one would expect for an amplifier simply matched for gain. However, noise performance has not been measured at this time. While the agreement between modeled vs. experimental data is not exact, the data prove that bump-bonded technology can be used for amplifiers at frequencies at least as high as 100 GHz. JPL is pursuing this technology as a way to economically and quickly incorporate the best available HEMTs into a circuit with all of the reliability and circuit design flexibility offered by MMIC technology. We are currently using the technology to fabricate 4-stage, wide-band, W-band LNA's. We have also performed pull and shear tests which show that the bump bonds are sufficiently robust for any anticipated application.

Pinsukanjana, Paul R.↗

A 90 GHz Amplifier Assembled Using Flip-Chip Technology

This letter reports the performance of a novel single-stage W-band amplifier fabricated utilizing flip-chip bump-bonding. We have bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) device onto a separately fabricated passive circuit having a GaAs substrate.

FET amplifiers Millimeter wave FETs bump-bonding m↗

Frequency to Voltage Converter Analog Front-End Prototype

The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

Mata, Carlos↗

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Zoutendyk, John A.↗

RF Reference Switch for Spaceflight Radiometer Calibration

The goal of this technology is to provide improved calibration and measurement sensitivity to the Soil Moisture Active Passive Mission (SMAP) radiometer. While RF switches have been used in the past to calibrate microwave radiometers, the switch used on SMAP employs several techniques uniquely tailored to the instrument requirements and passive remote-sensing in general to improve radiometer performance. Measurement error and sensitivity are improved by employing techniques to reduce thermal gradients within the device, reduce insertion loss during antenna observations, increase insertion loss temporal stability, and increase rejection of radar and RFI (radio-frequency interference) signals during calibration. The two legs of the single-pole double-throw reference switch employ three PIN diodes per leg in a parallel-shunt configuration to minimize insertion loss and increase stability while exceeding rejection requirements at 1,413 MHz. The high-speed packaged diodes are selected to minimize junction capacitance and resistance while ensuring the parallel devices have very similar I-V curves. Switch rejection is improved by adding high-impedance quarter-wave tapers before and after the diodes, along with replacing the ground via of one diode per leg with an open circuit stub. Errors due to thermal gradients in the switch are reduced by embedding the 50-ohm reference load within the switch, along with using a 0.25-in. (approximately equal to 0.6-cm) aluminum prebacked substrate. Previous spaceflight microwave radiometers did not embed the reference load and thermocouple directly within the calibration switch. In doing so, the SMAP switch reduces error caused by thermal gradients between the load and switch. Thermal issues are further reduced by moving the custom, highspeed regulated driver circuit to a physically separate PWB (printed wiring board). Regarding RF performance, previous spaceflight reference switches have not employed high-impedance tapers to improve rejection. The use of open-circuit stubs instead of a via to provide an improved RF short is unique to this design. The stubs are easily tunable to provide high rejection at specific frequencies while maintaining very low insertion loss in-band.

Knuble, Joseph↗

Multifunction Vacuum Chamber for IC Metallization

Vacuum system chamber processing multilayer metallization on integrated circuits (IC's) performs four operations ordinarily done in separated equipment. Chamber etches holes, removes photoresist, cleans by sputter etching, and deposits final layer of metal. Combinedfunction chamber costs less than separate equipment. Chamber avoids exposing integrated circuits to room air and, to oxidation and dust, between steps. Eliminates time spent in transferring circuits from one apparatus to next.

Routh, D. E.↗

Magnetically switched power supply system for lasers

A laser power supply system is described in which separate pulses are utilized to avalanche ionize the gas within the laser and then produce a sustained discharge to cause the gas to emit light energy. A pulsed voltage source is used to charge a storage device such as a distributed capacitance. A transmission line or other suitable electrical conductor connects the storage device to the laser. A saturable inductor switch is coupled in the transmission line for containing the energy within the storage device until the voltage level across the storage device reaches a predetermined level, which level is less than that required to avalanche ionize the gas. An avalanche ionization pulse generating circuit is coupled to the laser for generating a high voltage pulse of sufficient amplitude to avalanche ionize the laser gas. Once the laser gas is avalanche ionized, the energy within the storage device is discharged through the saturable inductor switch into the laser to provide the sustained discharge. The avalanche ionization generating circuit may include a separate voltage source which is connected across the laser or may be in the form of a voltage multiplier circuit connected between the storage device and the laser.

Pacala, Thomas J.↗

Method for reducing snap in magnetic amplifiers

Method of reducing snap in magnetic amplifiers uses a degenerative feedback circuit consisting of a resistor and a separate winding on a magnetic core. The feedback circuit extends amplifier range by allowing it to be used at lower values of output current.

Fischer, R. L. E.↗

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, TImothy M.↗

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit paths by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabricated parts were hybridized using a flip-chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, Timothy M.↗

Enabling Large Focal Plane Arrays Through Mosaic Hybridization

We have demonstrated advances in mosaic hybridization that will enable very large format far-infrared detectors. Specifically we have produced electrical detector models via mosaic hybridization yielding superconducting circuit patbs by hybridizing separately fabricated sub-units onto a single detector unit. The detector model was made on a 100mm diameter wafer while four model readout quadrant chips were made from a separate 100mm wafer. The individually fabric.ted parts were hybridized using a Suss FCI50 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the model mosaic-hybrid detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently available.

Miller, Timothy M.↗

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Burns, Michael J.↗

Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Burns, Michael J.↗

Carrier extraction circuit

Feedback loop extracts demodulated reference signals from IF input and feeds signal back to demodulator. Since reference signal is extracted directly from carrier, no separate reference need be transmitted. Circuit obtains coherent carrier from balanced or unbalanced four-phase signal of varying characteristics.

Solomon, K.↗

Development of a monolithic GaAs integrated optical transmitter

The paper discusses a program designed for the development of a GaAs IOC transmitter consisting of a monolithic surface laser whose output is coupled into patterned channel waveguides. Modulation and switching of the radiation occur in the waveguide circuit and are controlled separately. These structures are to be fabricated monolithically on a single semiconductor chip with each device amenable to integrated low-cost manufacture. The waveguide outputs of the IOC transmitter will be coupled to single mode optical fibers which form a transmission cable. The properties of the semiconductors (Ga,Al)As and (Ga,In)As permit performance of each of the basic functions included in the device considered. The concept of monolithic nondiscrete GaAs diode lasers is examined along with optical stripline channel waveguides and electro-optic channel waveguide modulators and switches.

Blum, F. A.↗

Electromechanical Nerve Stimulator

Nerve stimulator applies and/or measures precisely controlled force and/or displacement to nerve so response of nerve measured. Consists of three major components connected in tandem: miniature probe with spherical tip; transducer; and actuator. Probe applies force to nerve, transducer measures force and sends feedback signal to control circuitry, and actuator positions force transducer and probe. Separate box houses control circuits and panel. Operator uses panel to select operating mode and parameters. Stimulator used in research to characterize behavior of nerve under various conditions of temperature, anesthesia, ventilation, and prior damage to nerve. Also used clinically to assess damage to nerve from disease or accident and to monitor response of nerve during surgery.

Tcheng, Ping↗

Improved Separators For Rechargeable Lithium Cells

Improved pairs of separators proposed for use in rechargeable lithium cells operating at ambient temperature. Block growth of lithium dendrites and help prevent short circuits. Each cell contains one separator made of microporous polypropylene placed next to anode, and one separator made of microporous polytetrafluoroethylene (PTFE) next to cathode. Separators increase cycle lives of secondary lithium cells. Cells to which concept applicable those of Li/TiS(2), Li/NbSe(3), Li/CoO(2), Li/MoS(2), Li/VO(x), and Li/MnO(2) chemical systems. Advantageous in spacecraft, military, communications, automotive, and other applications in which high energy density and rechargeability needed.

Shen, David↗

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.

Rao, Hariprasad Nannapaneni↗