Final Report
Explore the source record for details and available documents.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
SEARCH · Engineering Papers
Results for “SOI CMOS”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Development of a CMOS Oscillator Chain for Particle Detection based on SOI technology
A new development of an oscillator concept, dedicated to the detection and tracking of particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. The very first solution was proposed using bulk technology. This new development is based on SOI technology what makes it tolerant to radiations. (authors)
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Enhanced spectroscopic gas sensors using in-situ grown carbon nanotubes
In this letter, we present a fully complementary-metal-oxide-semiconductor (CMOS) compatible microelectromechanical system thermopile infrared (IR) detector employing vertically aligned multi-walled carbon nanotubes (CNT) as an advanced nano-engineered radiation absorbing material. The detector was fabricated using a commercial silicon-on-insulator (SOI) process with tungsten metallization, comprising a silicon thermopile and a tungsten resistive micro-heater, both embedded within a dielectric membrane formed by a deep-reactive ion etch following CMOS processing. In-situ CNT growth on the device was achieved by direct thermal chemical vapour deposition using the integrated micro-heater as a micro-reactor. The growth of the CNT absorption layer was verified through scanning electron microscopy, transmission electron microscopy, and Raman spectroscopy. The functional effects of the nanostructured ad-layer were assessed by comparing CNT-coated thermopiles to uncoated thermopiles. Fourier transform IR spectroscopy showed that the radiation absorbing properties of the CNT adlayer significantly enhanced the absorptivity, compared with the uncoated thermopile, across the IR spectrum (3 μm–15.5 μm). This led to a four-fold amplification of the detected infrared signal (4.26 μm) in a CO{sub 2} non-dispersive-IR gas sensor system. The presence of the CNT layer was shown not to degrade the robustness of the uncoated devices, whilst the 50% modulation depth of the detector was only marginally reduced by 1.5 Hz. Moreover, we find that the 50% normalized absorption angular profile is subsequently more collimated by 8°. Our results demonstrate the viability of a CNT-based SOI CMOS IR sensor for low cost air quality monitoring.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design
After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Advanced CMOS Radiation Effects Testing and Analysis
Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.
cmos↗
Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration
The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation
operational amplifier↗
Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies
We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies
single-event effects↗
Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies
We report low-energy proton and low-energy alpha particle single-event effects (SEE) data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latches and static random access memory (SRAM) that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 megaelectron-volt. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.
random access memory↗
High Linearity RF Circuits in CMOS Platforms (CRADA Final Report)
The goal of this CRADA was to understand high linearity silicon-on-insulator (SOI) radio frequency switches. The first direction investigated was high linearity RF mixers as these components are composed of a network of switches. During the course of the investigation, it was determined that while the SOI RF switches were effective in the application in mixers and produced state of the art performance, the use of SOI for mixers is not economically feasible because the technology only worked with advanced CMOS nodes <65nm which can have an NRE cost (from lithography masks) in excess of $\$$500,000.
42 ENGINEERING↗
PDSOI and Radiation Effects: An Overview
Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.
Forgione, Joshua B.↗
Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K
Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.
circuit modeling↗
Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors
SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.
Irom, Farokh↗
Methods of producing strain in a semiconductor waveguide and related devices
Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.
36 MATERIALS SCIENCE↗
Slow-Light Mid-IR Silicon Photonic Chips for NO 2 and CH 4 Gas Detection
A compact, chip-scale mid-infrared gas sensor is demonstrated, leveraging a two-dimensional photonic crystal waveguide (PCW) fabricated on a silicon-on-insulator (SOI) platform. The PCW comprises a hexagonal lattice with lattice constant a = 860 nm and hole radius r = 0.22a, incorporating a central line defect of reduced-radius holes (r s = 0.7r) to induce slow-light propagation near the photonic band edge with a group index of approximately 73, thereby enhancing light-matter interaction. The sensor operates at fundamental absorption wavelengths of 3.42 μm for nitrogen dioxide (NO 2 ) and 3.40 μm for methane (CH 4 ), utilizing the strongest molecular vibrational transitions for maximum sensitivity. Experimental validation was conducted using dynamically diluted gas mixtures generated by mass flow controllers, with signal acquisition performed by a liquid nitrogen-cooled InSb detector. For NO 2 , the sensor exhibited excellent linear response over 5–25 ppm (part per million) with coefficient of determination R 2 = 0.9934, achieving a detection limit of 210 ppb (part per billion)─representing the first reported silicon photonic-based NO 2 detection. For CH 4 , exposure to 25 ppm resulted in a 6.4% decrease in transmitted intensity, demonstrating multigas sensing capability. The CMOS-compatible fabrication process and compact 3 mm device footprint establish this SOI-PCW platform as a scalable, low-power solution for integrated mid-infrared gas sensing, with significant potential for environmental monitoring and industrial safety applications.
Crystals↗
III-V/Si on silicon-on-insulator platform for hybrid nanoelectronics
The unique properties of SOI wafers enable the integration of heterogeneous materials with distinct functionalities in different layers. In particular, III-V compound semiconductors are very attractive for low-noise and high-speed electronic and photonic components integrated on a single chip. We have developed a CMOS compatible and fully integrated solution for the integration of III-V compound semiconductors with silicon technology for optoelectronic applications. InAs compound semiconductor nanostructures are synthesized in SOI wafers using the combined ion beam implantation and millisecond liquid-phase epitaxial growth. Optoelectronic and microstructural investigations carried out on implanted, annealed, and selectively etched samples confirm the formation of high-quality III-V compound semiconductor nanostructures.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Introduction of performance boosters like Ge as channel material for the future of CMOS
High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge is one of new attractive channel materials that require CMOS scaling For future technology nodes and future high performance P-MOSFETS, we have studied a nanoscale SOI DG MOSFETs using quantum simulation approach on DG MOSFETs within the variation of Ge channel concentration and in the presence of source and drain doping by replacing Silicon in the channel by Ge using various dielectric constant. The use of high mobility channel (like Ge) to maximize the MOSFET IDsat and simultaneously circumvent the poor electrostatic control to suppress short-channel effects and enhance source injection velocity. The leakage current (I{sub off}) can be controlled by different gates oxide thickness more ever the required threshold voltage (V{sub TH}) can be achieved by keeping gate work function and altering the doping channel.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Nano-Multiplication-Region Avalanche Photodiodes and Arrays
Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.
Zheng, Xinyu↗
Buried Oxide Densification for Low Power, Low Voltage CMOS Applications
Special technology and circuit architecture are of growing interest for implementation of circuits which operate at low supply voltages and consume low power levels without sacrificing performance[1]. Use of thin buried oxide SOI substrates is a primary approach to simultaneously achieve these goals. A significant aspect regarding SIMOX SOI for low voltage, low power applications is the reliability and performance of the thin buried oxide. In addition, when subjected to high total dose irradiation, the silicon islands within the BOX layer of SIMOX can store charges and significantly effect the back channel threshold voltages of devices. Thus, elimination of the islands within the buried oxide (BOX) layer is preferred in order to prevent leakage through these conductive islands and charge build-up within the buried oxide layer. A differential (2-step) ramp rate as applied to full and 100 nm BOX SIMOX was previously reported to play a significant role in the stoichiometry and island formation within the buried layer[2]. This paper focus is on the properties of a thin (120nm) buried oxide as a function of the anneal ramp rate and the temperature of anneal. In this research, we have found an improvement in the buried oxide stoichiometry with the use of a slower, singular ramp rate for specified thin buried oxides, with slower ramp rates and higher temperatures of anneal suggested for reducing the presence of Si islands within the BOX layer.
Allen, L. P.↗