Binary magnetic memory device Patent
Nondestructive interrogating and state changing circuit for binary magnetic storage elements
Schaefer, D. H.↗
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Results for “Memory device”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Investigation of fluctuations in angular velocity in magnetic memory devices
The fluctuations in the angular velocity of individual assemblies of a precision mechanical system were analyzed. The system was composed of an electric motor and a magnetic drum which were connected by a flexible coupling. A dynamic model was constructed which took into account the absence of torsion in the rigid shafts of the electric motor drive rotor and the magnetic drum. The motion was described by Lagrange differential equations of the second kind. Curves are developed to show the nature of amplitude fluctuation of the magnetic drum angular velocity at a specific excitation frequency. Additional curves show the amplitudes of fluctuation of the magnetic drum angular velocity compared to the quantity of damping at specific frequencies.
Meshkis, Y. A.↗
Stripe-line coil for magnetic-field generation in bubble memory devices
Coil etched from conductive film has better field uniformity than wire-wound coils and less coil loss at high-frequency operation.
Chen, T. T.↗
Double Data Rate (DDR) Memory Devices
This presentation will include information about Double Data Rate (DDR) technology, NASA Electronic Parts and Packaging (NEPP) tasks and their purpose, collaborations, a roadmap, NEPP partners, results to date, and future plans.
NASA Electronic Parts and Packaging (NEPP) Program↗
Test and Assurance of Non-Volatile Memory Devices for Space
Explore the source record for details and available documents.
Ted Wilcox↗
Method and apparatus for data protection in memory devices
An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.
SeyedzadehDelcheh, SeyedMohammad↗
Investigation of new concepts of adaptive devices
Memory device whose threshold voltage can be altered reproducibly by applied voltage pulse
Wegener, H. A. R.↗
High-performance ultra-low power VLSI analog processor for data compression
An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.
Tawel, Raoul↗
A visual-display and storage device
Memory and display device uses cathodochromic material to store visual information and fast phosphor to recall information for display and electronic processing. Cathodochromic material changes color when bombarded with electrons, and is restored to its original color when exposed to light of appropiate wavelength.
Bosomworth, D. R.↗
Memory access statistics monitoring
Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
Roberts, David A.↗
Research on a non-destructive fluidic storage control device
Fluidic memory device with associated fluidic alpha numerical display
DISPLAY SYSTEM↗
Antiferromagnetic memory storage devices from magnetic transition metal dichalcogenides
Switchable antiferromagnetic (AFM) memory devices are provided based on magnetically intercalated transition metal dichalcogenides (TMDs) of the form AxMC2, where A is a magnetic element of stoichiometry x between 0 and 1, M is a transition metal of stoichiometry 1, and C is a chalcogen of stoichiometry 2. Memory storage is achieved by fabricating these materials into crosses of two or more bars and driving DC current pulses along the bars to rotate the AFM order to a fixed angle with respect to the current pulse. Application of current pulses along different bars can switch the AFM order between multiple directions. Standard resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by the input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.
Analytis, James G.↗
GaN-based threshold switching device and memory diode
A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.
Fu, Kai↗
GaN-based threshold switching device and memory diode
A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.
Fu, Kai↗
A Novel 3D DRAM Memory Cube Architecture for Space Applications
The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.
Yang-Scharlotta, Jean↗
Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite
The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.
MacLeond, Todd C.↗
Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order
A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.
Wulf, William A.↗
Nanoscale content-addressable memory
A combined content addressable memory device and memory interface is provided. The combined device and interface includes one or more one molecular wire crossbar memories having spaced-apart key nanowires, spaced-apart value nanowires adjacent to the key nanowires, and configurable switches between the key nanowires and the value nanowires. The combination further includes a key microwire-nanowire grid (key MNG) electrically connected to the spaced-apart key nanowires, and a value microwire-nanowire grid (value MNG) electrically connected to the spaced-apart value nanowires. A key or value MNGs selects multiple nanowires for a given key or value.
Davis, Bryan↗