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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Neurocontrol and fuzzy logic: Connections and designs

Artificial neural networks (ANNs) and fuzzy logic are complementary technologies. ANNs extract information from systems to be learned or controlled, while fuzzy techniques mainly use verbal information from experts. Ideally, both sources of information should be combined. For example, one can learn rules in a hybrid fashion, and then calibrate them for better whole-system performance. ANNs offer universal approximation theorems, pedagogical advantages, very high-throughput hardware, and links to neurophysiology. Neurocontrol - the use of ANNs to directly control motors or actuators, etc. - uses five generalized designs, related to control theory, which can work on fuzzy logic systems as well as ANNs. These designs can copy what experts do instead of what they say, learn to track trajectories, generalize adaptive control, and maximize performance or minimize cost over time, even in noisy environments. Design tradeoffs and future directions are discussed throughout.

Werbos, Paul J.↗
NASA NTRS1997

Free Flight and Self-Separation from the Flight Deck Perspective

The concept of "free flight", while still being developed, is intended to emphasize more, flexibility for operators in the National Airspace System (NAS) by providing more separation responsibility to pilots, New technologies, procedures, and concepts have been suggested by the aviation community to enable this task; however, much work needs to be accomplished to help define and evaluate the concept feasibility. The purpose of this simulation was to begin examining some of the communication and procedural issues associated with self-separation in the enroute environment. A simulation demonstration was conducted in the Boeing 747-400 simulator at NASA Ames Research Center. Commercial pilots (from a U.S. domestic carrier) current on the B747-400 aircraft were the participants. Ten flight crews (10 captains, 10 first officers) flew in the Denver enroute airspace environment. A new alerting logic designed to allow for airborne self-separation was created for this demonstration. This logic assumes automatic dependent surveillance broadcast (ADS-B) capability and represented aircraft up to 120 nautical miles on the display. The new flight deck display features were designed and incorporated on the existing navigational display in the simulator to allow for increased traffic and maneuvering information to the flight crew. New tools were also provided to allow the crews to assess conflicts and potential maneuvers before implementing them. Each of the flight crews flew eight different scenarios in the Denver enroute airspace. The scenarios included eight to ten other aircraft, and each scenario was created with the intent of having one of the other aircraft become an operational conflict for our simulator aircraft. Different types of conflict geometries were represented across the eight scenarios. Also, some scenarios allowed for more time to detect a potential clearance, while others allowed for less time for'detection. Additionally, the crews were asked to a ply the Visual Flight Rules (VFR) right of way rules when determining who should maneuver in a conflict situation; therefore, the scenarios were designed to test different applications of those recommendations, Data analyses include an evaluation of crew procedures and communication. The application of the VFR right-of-way rules are being explored. Timing variables are being examined to determine potential efficiency differences between scenarios and conflict types. Proximity of aircraft will be assessed as one indication of the operational safety. The intent of these evaluations is to help provide definitions and guidelines of negotiation procedures in a self-separation environment assuming automated data link technology (ADS-B). Also, definitions of likely flight crew maneuvers and application to current VFR right-of-way rules may be obtained, along with guidelines for negotiation procedures between flight crews.

Lozito, Sandra↗
NASA NTRS1988

Evaluation of a three-dimensional empirically derived wing at supersonic speeds

A novel wing design concept is introduced which takes advantage of the existence of conical flow at supersonic speeds. The present wing design concept is to create a near conical wing geometry by redistributing airfoils in a spanwise direction. In addition, a set of graphs which review the supersonic aerodynamics of delta wings have been employed to select a design wing sweep and Mach number. An iteration through the wing design logic resulted in the selection of a 65 deg swept delta wing and a design Mach number of 1.62. Theoretical analysis was performed with a nonlinear full-potential analysis method to assess the merits of the wing design approach. The analysis showed large reductions in drag due to lift compared to delta wings configured with traditional thickness and airfoil distributions.

Wood, Richard M.↗
NASA NTRS2004

Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration

Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.

digital circuits designs↗
NASA NTRS2008

Pratt and Whitney Overview and Advanced Health Management Program

Hardware Development Activity: Design and Test Custom Multi-layer Circuit Boards for use in the Fault Emulation Unit; Logic design performed using VHDL; Layout power system for lab hardware; Work lab issues with software developers and software testers; Interface with Engine Systems personnel with performance of Engine hardware components; Perform off nominal testing with new engine hardware.

Inabinett, Calvin↗
NASA NTRS1972

Two autowire versions for CDC-3200 and IBM-360

Microelectronics program was initiated to evaluate circuitry, packaging methods, and fabrication approaches necessary to produce completely procured logic system. Two autowire programs were developed for CDC-3200 and IBM-360 computers for use in designing logic systems.

Billingsley, J. B.↗
NASA NTRS1991

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Source record↗
NASA NTRS2013

Formal Validation of Fault Management Design Solutions

The work presented in this paper describes an approach used to develop SysML modeling patterns to express the behavior of fault protection, test the model's logic by performing fault injection simulations, and verify the fault protection system's logical design via model checking. A representative example, using a subset of the fault protection design for the Soil Moisture Active-Passive (SMAP) system, was modeled with SysML State Machines and JavaScript as Action Language. The SysML model captures interactions between relevant system components and system behavior abstractions (mode managers, error monitors, fault protection engine, and devices/switches). Development of a method to implement verifiable and lightweight executable fault protection models enables future missions to have access to larger fault test domains and verifiable design patterns. A tool-chain to transform the SysML model to jpf-Statechart compliant Java code and then verify the generated code via model checking was established. Conclusions and lessons learned from this work are also described, as well as potential avenues for further research and development.

Statechart↗
NASA NTRS2000

Asynchronous FPGA risks

The worst case timing margin of a synchronous design implemented with a field-programmable gate array (FPGA) is easy to perform using available FPGA design tools. However, it may be difficult to impossible to verify that worst case timing requirements are met for complex asynchronous logic design.

risk FPGA asynchronous↗
NASA NTRS1990

Implications of Tracey's theorem to asynchronous sequential circuit design

Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.

Gopalakrishnan, S.↗
NASA NTRS1993

Partition algebraic design of asynchronous sequential circuits

Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that partitioning variables derived from Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.

Maki, Gary K.↗
NASA NTRS1989

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗
NASA NTRS1980

F100 multivariable control synthesis program: A review of full scale engine altitude tests

The benefits of linear quadratic regulator synthesis methods in designing a multivariable engine control capable of operating an engine throughout its flight envelope were demonstrated. The entire multivariable control synthesis program is reviewed with particular emphasis on engine tests conducted in the NASA Lewis propulsion systems laboratory altitude facility. The multivariable control has basically a proportional plus integral, model following structure with gains scheduled as functions of flight condition. The multivariable control logic design is described, along with control computer implementation aspects. Altitude tests demonstrated that the multivariable control logic could control an engine over a wide range of test conditions. Representative transient responses are presented to demonstrate engine behavior and the functioning of the control logic.

Lehtinen, B.↗
NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗
NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS1982

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented.

Lam, A. Y.↗