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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

PLATO (Parallel Load Assignment Tool): A Parallel Workload Partitioner for Particle-based Methods

A key first step in many large-scale high-performance scientific computing applications is the distribution of the computational domain across all participating processors of a parallel computing platform such as a shared memory machine, cluster or a tightly-coupled supercomputer. The primary goal of such a partitioning step is to ensure that the computational work performed by each process remains load-balanced throughout the execution of the parallel application. In this project, a general-purpose parallel partitioning tool, code-named PLATO, was designed and implemented. PLATO assumes that the workload is a set of points in an n-dimensional metric space. These points are abstractions of computational units that may represent point-like computational units such as celestial objects in astrophysics, atoms in materials sciences and molecules in biology/chemistry, or may represent more abstract computational units such as grid points in finite difference methods, grid elements in finite element methods or n-dimensional points in the feature space of a host of other applications. PLATO supports several key and useful capabilities, namely: (a) multiple load partitioning strategies, (b) support for arbitrary user-defined processor topology, (c) pre-fetching data from neighboring processors based on user-defined parameters, and (d) support for arbitrary number and types of attributes associated with each point in the computational domain. PLATO is implemented in the C programming language using Message Passing Interface (MPI) for inter-processor communications and its parallel performance tested on up to 48 processors of a shared memory machine. This report includes a detailed performance study of PLATO using parallel speedup and iso-efficiency as the two main metrics of parallel performance. In addition, a user manual and DOXYGEN generated code documentation have been included for completeness.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Assessment of Multi-Scale Thermal-Hydraulic Codes and Models for DNB Challenge Problem Applications

The objectives of this milestone work are to assess the improved capabilities of the multi-scale thermal-hydraulic (T/H) codes and models developed by the Consortium for Advanced Simulation of Light Water Reactors (CASL) for Departure from Nucleate Boiling (DNB) Challenge Problem (CP), in accordance with the DNB CP implementation plan. The multi-scale models can range from fine mesh Computational Fluid Dynamics (CFD) simulation of flow field surrounding a fuel rod to a full core modeling of a Pressurized Water Reactor (PWR). The assessments are performed based on the CASL subchannel code COBRA-TF (CTF) and the CFD code Hydra-TH. Significant improvements have been achieved on the CASL multi-scale T/H code and modeling capabilities based on the CTF subchannel code and the Hydra-TH CFD code in the past year for DNB CP applications. The improvements are reflected in the new transient modeling for the Reactivity Insertion Accident (RIA) DNB predictions and full assembly modeling using the CTF code and its processor, as well as the rod bundle modeling for single-phase flow and heat transfer simulations using the Hydra-TH code, the pre-processor for mesh generation and the post-processor for data visualization.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2014

Automated cassette-to-cassette substrate handling system

An automated cassette-to-cassette substrate handling system includes a cassette storage module for storing a plurality of substrates in cassettes before and after processing. A substrate carrier storage module stores a plurality of substrate carriers. A substrate carrier loading/unloading module loads substrates from the cassette storage module onto the plurality of substrate carriers and unloads substrates from the plurality of substrate carriers to the cassette storage module. A transport mechanism transports the plurality of substrates between the cassette storage module and the plurality of substrate carriers and transports the plurality of substrate carriers between the substrate carrier loading/unloading module and a processing chamber. A vision system recognizes recesses in the plurality of substrate carriers corresponding to empty substrate positions in the substrate carrier. A processor receives data from the vision system and instructs the transport mechanism to transport substrates to positions on the substrate carrier in response to the received data.

47 OTHER INSTRUMENTATION↗
DOE OSTI2015

The overvoltage protection module for the power supply system for the pixel detector at Belle II experiment at KEK

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experiment as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2017

Active non-volatile memory post-processing

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Dynamic cache bypassing

A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Per-instruction energy debugging using instruction sampling hardware

A processor utilizes instruction based sampling to generate sampling data sampled on a per instruction basis during execution of an instruction. The sampling data indicates what processor hardware was used due to the execution of the instruction. Software receives the sampling data and generates an estimate of energy used by the instruction based on the sampling data. The sampling data may include microarchitectural events and the energy estimate utilizes a base energy amount corresponding to the instruction executed along with energy amounts corresponding to the microarchitectural events in the sampling data. The sampling data may include switching events associated with hardware blocks that switched due to execution of the instruction and the energy estimate for the instruction is based on the switching events and capacitance estimates associated with the hardware blocks.

Wei, Shijia↗
DOE OSTI2019

Error detection and correction utilizing locally stored parity information

A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Mixed core processor unit

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

PAGANI: a parallel adaptive GPU algorithm for numerical integration

We present a new adaptive parallel algorithm for the challenging problem of multi-dimensional numerical integration on massively parallel architectures. Adaptive algorithms have demonstrated the best performance, but efficient many-core utilization is difficult to achieve because the adaptive work-load can vary greatly across the integration space and is impossible to predict a priori. Existing parallel algorithms utilize sequential computations on independent processors, which results in bottlenecks due to the need for data redistribution and processor synchronization. Our algorithm employs a high-throughput approach in which all existing sub-regions are processed and sub-divided in parallel. Repeated sub-region classification and filtering improves upon a brute-force approach and allows the algorithm to make efficient use of computation and memory resources. A CUDA implementation shows orders of magnitude speedup over the fastest open-source CPU method and extends the achievable accuracy for difficult integrands. Our algorithm typically outperforms other existing deterministic parallel methods.

Sakiotis, Ioannis↗
DOE OSTI2015

A Client/Server Architecture for Supporting Science Data Using EPICS Version 4

The Phase 1 grant that serves as a precursor to this proposal, prototyped complex storage techniques for high speed structured data that is being produced in accelerator diagnostics and beam line experiments. It demonstrates the technologies that can be used to archive and retrieve complex data structures and provide the performance required by our new accelerators, instrumentations, and detectors. Phase 2 is proposed to develop a high-performance platform for data acquisition and analysis to provide physicists and operators a better understanding of the beam dynamics. This proposal includes developing a platform for reading 109 MHz data at 10 KHz rates through a multicore front end processor, archiving the data to an archive repository that is then indexed for fast retrieval. The data is then retrieved from this data archive, integrated with the scalar data, to provide data sets to client applications for analysis, use in feedback, and to aid in identifying problem with the instrumentation, plant, beam steering, or model. This development is built on EPICS version 4 , which is being successfully deployed to implement physics applications. Through prior SBIR grants, EPICS version 4 has a solid communication protocol for middle layer services (PVAccess), structured data representation and methods for efficient transportation and access (PVData), an operational hierarchical record environment (JAVA IOC), and prototypes for standard structured data (Normative Types). This work was further developed through project funding to successfully deploy the first service based physics application environment with demonstrated services that provide arbitrary object views, save sets, model, lattice, and unit conversion. Thin client physics applications have been developed in Python that implement quad centering, orbit display, bump control, and slow orbit feedback. This service based architecture has provided a very modular and robust environment that enables commissioning teams to rapidly develop and deploy small scripts that build on powerful services. These services are all built on relational database data stores and scalar data. The work proposed herein, builds on these previous successes to provide data acquisition of high speed data for online analysis clients.

43 PARTICLE ACCELERATORS↗
DOE OSTI2019

Collective memory transfer devices and methods for multiple-core processors

This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Development of a reduced model for energetic particle transport by sawteeth in tokamaks

We report that the sawtooth instability is known for inducing transport and loss of energetic particles (EPs), and for generating seed magnetic islands that can trigger tearing modes. Both effects degrade the overall plasma performance. Several theories and numerical models have been previously developed to quantify the expected EP transport caused by sawteeth, with various degrees of sophistication to differentiate the response of EPs at different energies and on different orbits (e.g. passing vs. trapped), although the analysis is frequently limited to a single time slice during a tokamak discharge. This work describes the development and initial benchmark of a framework that enables a reduced model for EP transport by sawteeth retaining the full EP phase-space information. The model, implemented in the ORBIT hamiltonian particle-following code, can be used either as a standalone post-processor taking input data from codes such as TRANSP, or as a pre-processor to compute transport coefficients that can be fed back to TRANSP for time-dependent simulations including the effects of sawteeth on EPs. The advantage of the latter approach is that the evolution of the EP distribution can be simulated quantitatively for sawtoothing discharges, thus enabling a more accurate modeling of sources, sinks and overall transport properties of EP and thermal plasma species for comprehensive physics studies that require detailed information of the fast-ion distribution function and its evolution over time.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2014

Domi

Domi (Greek for "structure") is a Trilinos package that provides support for multi-dimensional data arrays distributed over multiple processors of a high performance computing system. The software supports data arrays of arbitrary number of dimensions mapped to a multi-dimensional grid of processors. Domi provides local access to the data, as well as the ability to compute global quantities such as norms, maxima and minima. Data arrays can be constructed with boundary and communication padding, necessary for finite difference algorithms, and provides high-level methods for communicating data between processors to update these buffers. The distributed maps and vectors in Domi can be converted to the equivalent data structures in Epetra and Tpetra (both of which assume unstructured data), using view semantics when appropriate, for use with other Trilinos solvers.

Spotz, WilliamF.↗
DOE OSTI2014

Domi

Domi (Greek for "structure") is a Trilinos package that provides support for multi-dimensional data arrays distributed over multiple processors of a high performance computing system. The software supports data arrays of arbitrary number of dimensions mapped to a multi-dimensional grid of processors. Domi provides local access to the data, as well as the ability to compute global quantities such as norms, maxima and minima. Data arrays can be constructed with boundary and communication padding, necessary for finite difference algorithms, and provides high-level methods for communicating data between processors to update these buffers. The distributed maps and vectors in Domi can be converted to the equivalent data structures in Epetra and Tpetra (both of which assume unstructured data), using view semantics when appropriate, for use with other Trilinos solvers.

Spotz, William F.↗
DOE OSTI2022

Vector-Matrix Multiplication Engine for Neuromorphic Computation with a CBRAM Crossbar Array [Slides]

The core function of many neural network algorithms is the dot product, or vector matrix multiply (VMM) operation. Crossbar arrays utilizing resistive memory elements can reduce computational energy in neural algorithms by up to five orders of magnitude compared to conventional CPUs. Moving data between a processor, SRAM, and DRAM dominates energy consumption. By utilizing analog operations to reduce data movement, resistive memory crossbars can enable processing of large amounts of data at lower energy than conventional memory architectures.

97 MATHEMATICS AND COMPUTING↗