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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

CMOS RAM cosmic-ray-induced-error-rate analysis

A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

Pickel, J. C.↗
NASA NTRS1984

Finding Open Faults In CMOS Circuits

Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.

Chandramouli, R.↗
NASA NTRS1983

Ambient and cryogenic temperature testing of a 32-channel CMOS multiplexer

A 32 channel CMOS multiplexer was tested at room temperature and at liquid helium temperature (4.9 K). Voltage gain of the FET input stage, leakage current, electrical crosstalk, and noise as a function of clock frequency were measured. The voltage gain measured at 4.9 K was slightly higher than that measured at 300 K and was independent of clock frequency at both operating temperatures. The off channel leakage current was 0.23 pA/channel at 4.9 K. Electrical crosstalk between adjacent channels (one on, one off) was quite low. The spot noise at 10 Hz, of the CMOS multiplexer operating in the static mode did not vary significantly with operating temperature. In the dynamic mode (3.2 kHz clock) at room temperature, the spot noise at 10 Hz was substantially higher than that measured in the static mode.

Lee, J. H.↗
NASA NTRS1982

On testing stuck-open faults in CMOS combinational circuits

Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.

Chandramouli, R.↗
NASA NTRS1985

The 1.2 micron CMOS technology

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.↗
NASA NTRS1986

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Cable, J. S.↗
NASA NTRS1988

Application of linear response theory to experimental data of simultaneous radiation and annealing response of a CMOS device

Results from the application of linear response theory are compared to experimental data from simultaneous radiation and annealing response of a CMOS device. In particular, a method is applied which was developed earlier to determine the characteristic time, t(0), as well as the parameters A and C in the 1n(t) dependence of the linear response function R(t) = -C + A1n(1-t/t(0)). The method is based on a study of the linear response for t being much less than t(0), when R(t) can be expanded in a power series of t: R(t) = R(0) + R'(0)t + 1/2R''(0)t-squared + 1/3R'''(0)t-cubed + ..., where R'(0) and R''(0) are, respectively, the first and second derivatives of R with respect to t. To find the linear response, R(t-t') is substituted in the form of this power series equation into a general equation for the shift of the threshold potential. To test the method, irradiation experiments were conducted on RCA 10(6) rad-hard CMOS IC's. A dose rate of approximately 130 rads/min was used. An IC was irradiated with Co-60 gamma rays for several hours, taking measurements of the threshold potential for one n-channel and one p-channel transistor every ten minutes. For the p-channel transistor, t(0) was found to be approximately 110 min and for the n-channel, t(0) was approximately 70 min. For the p-channel, the theoretical curve deviates from the experimental points only after 70 min; for the n-channel, the deviation takes place after 45 min. Additional findings are discussed and the application of the method to pure annealing is described.

Litovchenko, V.↗
NASA NTRS1988

Optical addressing technique for a CMOS RAM

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Wu, W. H.↗
NASA NTRS1988

CMOS Process Monitor

A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.

Buehler, M. G.↗
NASA NTRS1990

Failures of CMOS Circuits Irradiated At Low Rates

Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

Goben, Charles A.↗
NASA NTRS1991

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗
NASA NTRS1990

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗
NASA NTRS1990

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗
NASA NTRS1991

Single phase dynamic CMOS PLA using charge sharing technique

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.↗
NASA NTRS1997

Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits

Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.

Bennett, K.↗
NASA NTRS2002

Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

Non-NASA Center↗
NASA NTRS1995

JPL CMOS Active Pixel Sensor Technology

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS1995

CMOS Image Sensors: Electronic Camera On A Chip

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Space Microelectronics Image Sensors APS Digital I↗