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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28

Low cost solar aray project: Experimental process system development unit for producing semiconductor-grade silicon using the silane-to-silicon process

This phase consists of the engineering design, fabrication, assembly, operation, economic analysis, and process support R&D for an Experimental Process System Development Unit (EPSDU). The mechanical bid package was issued and the bid responses are under evaluation. Similarly, the electrical bid package was issued, however, responses are not yet due. The majority of all equipment is on order or has been received at the EPSDU site. The pyrolysis/consolidation process design package was issued. Preparation of process and instrumentation diagram for the free-space reactor was started. In the area of melting/consolidation, Kayex successfully melted chunk silicon and have produced silicon shot. The free-space reactor powder was successfully transported pneumatically from a storage bin to the auger feeder twenty-five feet up and was melted. The fluid-bed PDU has successfully operated at silane feed concentrations up to 21%. The writing of the operating manual has started. Overall, the design phase is nearing completion.

Source record↗

Electronic Packaging Techniques

A characteristic of aerospace system design is that equipment size and weight must always be kept to a minimum, even in small components such as electronic packages. The dictates of spacecraft design have spawned a number of high-density packaging techniques, among them methods of connecting circuits in printed wiring boards by processes called stitchbond welding and parallel gap welding. These processes help designers compress more components into less space; they also afford weight savings and lower production costs.

Source record↗

Piggy-back mounting would increase microcircuit packaging density

Piggy-back method of packaging integrated circuits will increase packaging density and design flexibility. It will also eliminate interconnection leads between the die and associated inductances, and thus increase the attainable frequency response of the circuit.

Gaudiano, S.↗

Fine pointing control, OAO-3

The fine error sensor located within the Princeton Experiment Package (PEP) is designed to aquire a star within its field of view to hold the spacecraft within plus or minus one-tenth of an arc second in pitch, and plus or minus three-arc seconds about the yaw axis. Pointing accuracy and stability tests of the fine error sensor exceeded the plus or minus 0.1 arc second requirement.

Moore, J. V.↗

Sensor equipment of the German earth scientific airplane program

The German airplane program for earth scientific research supports the work of a vast staff of earth scientists from universities and federal agencies. Due to their fields of interest, which are in oceanography, hydrology, geology, ecology, and forestry, five test areas were selected which are spread all over Germany. The sensor package, which was designed in accordance with the requirements of this group of scientists, will be installed in a DO 28 D2 type airplane. The sensor equipment consists of a series of 70-mm cameras having different film/filter combinations, a photogrammetric camera, an infrared radiometer, an 11-channel multispectral line scanner, a LANDSAT-compatible radiometer, and a complex avionic system. Along with the airplane, a truck will be equipped with a set of radiometers and other sensor devices for extensive ground-truth measurement; this also includes a cherry picker.

Seige, P.↗

A methodology for the evaluation of program cost and schedule risk for the SEASAT program

An interactive computerized project management software package (RISKNET) is designed to analyze the effect of the risk involved in each specific activity on the results of the total SEASAT-A program. Both the time and the cost of each distinct activity can be modeled with an uncertainty interval so as to provide the project manager with not only the expected time and cost for the completion of the total program, but also with the expected range of costs corresponding to any desired level of significance. The nature of the SEASAT-A program is described. The capabilities of RISKNET and the implementation plan of a RISKNET analysis for the development of SEASAT-A are presented.

Abram, P.↗

HEPP - A low temperature Heat Pipe Experiment Package developed for flight on-board the Long Duration Exposure Facility /LDEF/

The Heat Pipe Experiment Package (HEPP) is designed to provide a flight evaluation system for low temperature heat pipes. The HEPP will be flown aboard the Long Duration Exposure Facility which will be launched and retrieved as part of the Space Shuttle program. The experiment contains two heat pipes: an axially grooved fixed conductance heat pipe and a liquid blockage thermal diode. A phase change material canister is also integrated with a radiant cooler system. Additional hardware consists of supporting electrical equipment, including electronics for signal conditioning and command functions, a data recorder, and a hermetically sealed battery which powers the experiment. A thermal model was developed to simulate the behavior of the HEPP and a ground test program was conducted to verify the predicted performance of the equipment.

Suelau, H. J.↗

CMOS circuit-fabrication handbook

Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.

Bouldin, D. L.↗

Real-time image enhancement

Pipelined system with "vision" algorithm is implemented on LSI chip that processes input digital image data to produce image-edge map. System contains 3 input adder, difference and absolute value cells, and adder and comparator. Data store for 1 to 2 ms, and are easily transmitted or isolated; design has reduced package count and number of interconnections for increased reliability. Applications include locating objects on moving belt, deep-sea and coal mining, and control of robotic rovers.

Wong, V. S.↗

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Bouldin, D. L.↗

Development of a simple, self-contained flight test data acquisition system

This paper describes a simple, self-contained flight test data acquisition system. The system makes use of the latest sensor and microprocessor technology available, to reduce overall system costs. Coupled with this is the use of modern control theory techniques allowing minimization of data requirements, as well as flight time requirements. Capability of the system includes primarily stability and performance analysis of general aviation airplanes, although system versatility has been designed into the package. Presented are details of the prototype system constructed, as well as details of the data reduction technique utilized. Preliminary results of the flight test program have also been included which demonstrate the capability of this system.

Renz, R. R. L.↗

Optimization of large area solar cells for low cost space application

The development of large-area solar cell manufacturing techniques for production of up to 10 kW/month of cells for use on the Shuttle Power Extension Package is detailed. Design goals for the cells were 14% efficiency at 135.3 mW/sq cm AM0 illumination for a 10 ohm-cm BSF/reflector cell, or 12.8% for a 2 ohm-cm BSR cell. Use of terrestrial cell technology to produce CVD SiO2 dielectric insulators for 3-in. ingot cells yielded satisfactory contact integrity. Fused silica coverings with thicknesses of 0.004 in. have allowed exploration of conventional and wraparound cell configurations due to inherent flexibilities of the frosted covers. One production run can now handle 108 3-in. wafers for the wraparound form or 216 in one-sided contact evaporations, with both processes taking 70 mins. Current contact grid designs for space use production permits average efficiencies of 12.8%.

Matthei, K. W.↗

A 20-GHz IMPATT diode development

The development of 20 GHz, double drift GaAs IMPATT diodes is described. Advances made in material growth, diodes fabrication technology and packaging, and circuit design and diode testing are documented.

Masse, D.↗

A basic design fault in ceramic flat packs

Recent moisture resistance tests of various multilayer top brazed ceramic flat packs and leaded and unleaded chip carriers has revealed a serious design defect. These packages, which utilize a tungsten interconnect system, in the presence of high humidity, suffer a galvanic corrosion which anodically consumes the tungsten. This process can continue until the package suffers an open circuit. The test results indicate that the lead plating system does not adequately seal off the interface area where the tungsten strips egresses from the inside of the package.

Drotman, B.↗