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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28

Low Temperature Operation of a Switching Power Converter

The low temperature operation of a 48 W, 50 kHz, 36/12 V pulse width modulated (PWM) buck de-de power converter designed with standard commercially available components and devices is reported. The efficiency of the converter increased from 85.6% at room temperature (300 K) to 92.0% at liquid nitrogen temperature (77 K). The variation of power MOSFET, diode rectifier, and output filter inductor loss with temperature is discussed. Relevant current, voltage. and power waveforms are also included.

Anglada-Sanchez, Carlos R.↗

An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

Jackson, S. A.↗

Simulation of Ultra-Small Electronic Devices: The Classical-Quantum Transition Region

Concern is increasing about how quantum effects will impact electronic device operation as down-scaling continues along the SIA Roadmap through 2010. This document describes part of a new semiconductor device modeling (SDM) program at NAS to investigate these concerns by utilizing advanced NAS and third-party numerical computation software to rapidly implement and investigate electronic device models including quantum effects. This SDM project will investigate quantum effects in devices in the classical-quantum transition region, especially sub-0.1 mm MOSFETs. Specific tasks planned for this project include the use of quantum corrections to the classical drift-diffusion and hydrodynamic models of electron transport, arid the use of nominally quantum models including significant scattering.

Biegel, Bryan A.↗

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Rafferty, Connor S.↗

Where is scattering important in nanotransistors?

This viewgraph presentation provides an overview of scattering in nanotransistors. Topics covered include: scattering mechanisms, devices used and series resistance. The authors conclude: (1) the influence of electron-photon scattering on the on-current of dual gate MOSFET's using the non-equilibrium Green's function method and (2) the influence of the drain extension region can no longer be modeled as a series resistance.

Anantram, M. P.↗

Analysis of Carbon Nanotube Field-Effect-Transistors (FETs)

This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.

Yamada, Toshishige↗

The four-gate transistor

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

neuro-prosthetic devices cortical signals↗

High Efficiency Synchronous Rectification in Spacecraft

This paper examines the implementaion of MOSFETs as synchronous rectifiers which results in a substantial improvement in power processing efficency and therefore may result in significant reduction of spacecraft mass and volum for the same payload.

Spacecraft Power↗

Observations on ion track structure in semiconductors : a phenomenological study

An ion track structure model at the nanometer scale is presented. The model is based on electrostatic principles and is supported by observed experimental results conducted on power MOSFETs. The model predicts the existence of a transient induced electric field following the passage of an energetic heavy ion. There are two segments to the field (a radial and an axial component). It is the interaction of this transient electric field with the local environment that can trigger a catastrophic failure.

SEGR↗

Power connect safety and connection interlock

A power connect safety and connection interlock system is shown for use with inverters and other DC loads (16) which include capacitor filter banks (14) at their DC inputs. A safety circuit (20) operates a spring (26) biased, solenoid (22) driven mechanical connection interference (24) which prevents mating and therefore electrical connection between the power contactor halves (11, 13) of the main power contacts (12) until the capacitor bank is safely precharged through auxiliary contacts (18). When the DC load (16) is shut down, the capacitor bank (14) is automatically discharged through a discharging power resistor (66) by a MOSFET transistor (60) through a discharging power resistor (66) only when both the main power contacts and auxiliary contacts are disconnected.

Rippel, Wally E.↗

Passively forced current sharing among transistors

This application concerns a simple passive circuit that improves current balance in paralleled power MOSFETs that are not precisely matched and that are operated in their active region from a common gate drive. A nonlinear circuit consisting of diodes and resistors generates a differential gate potential required to correct for unbalance while maintaining low losses over a range of current.

Niedra, Janis M.↗

Methods for growth of relatively large step-free SiC crystal surfaces

A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.

Neudeck, Philip G.↗

Ultra low-noise charge coupled device

Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

Janesick, James R.↗

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗