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At least 487 records · Page 27

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NASA NTRS1986

Versatile simulation testbed for rotorcraft speech I/O system design

A versatile simulation testbed for the design of a rotorcraft speech I/O system is described in detail. The testbed will be used to evaluate alternative implementations of synthesized speech displays and speech recognition controls for the next generation of Army helicopters including the LHX. The message delivery logic is discussed as well as the message structure, the speech recognizer command structure and features, feedback from the recognizer, and random access to controls via speech command.

Simpson, Carol A.↗

NASA NTRS1987

A neurocomputer based on an analog-digital hybrid architecture

A novel analog-digital hybrid architecture based on the utilization of high density digital random access memories for the storage of the synaptic weights of a neural network, and high speed analog hardware to perform neural computation is described. An electronic neurocomputer based on such an architecture is ideally suited for investigating the dynamics, associative recall properties, and computational capabilities of neural networks and provides significant speed improvement in comparison to conventional software based neural network simulations. As a demonstration of the feasibility of the hybrid architectural concept, a prototype breadboard hybrid neurocomputer system with 32 neurons has been designed and fabricated with off-the-shelf hardware components. The performance of the breadboard system has been tested for variety of applications including associative memory and combinatorial problem solving such as Graph Coloring, and is discussed in this paper.

Moopenn, A.↗

NASA NTRS1988

Characterization of direct readout Si:Sb and Si:Ga infrared detector arrays for space-based astronomy

Preliminary test results from the evaluation of Si:Sb and Si:Ga 58 x 62-element infrared detector arrays are presented. These devices are being characterized under background conditions and readout rates representative of operation in orbiting, crogenically-cooled infrared observatories. The arrays are hybridized to silicon direct-readout multiplexers which allow random-access and nondestructive readout. Array performance optimization is being conducted with a flexible microcomputer-based drive and readoaut electronics system. Preliminary Si:Sb measurements indicate a sense node capacitance of 0.06 pF, peak (28-micron) responsivity above 3 A/W at 2V bias, read noise of 130 rms e(-), dark current approximately 10 e(-)/s, and a well capacity greater than 10 to the 5th e(-). The limited test data available on the performance of the Si:Ga array are also discussed.

Mckelvey, Mark E.↗

NASA NTRS1989

Optical Addressing And Clocking Of RAM's

Proposed random-access-memory (RAM) addressing system, in which memory linked optically to read/write logic circuits, greatly increases computer operating speed. System - comprises addressing circuits including numerous lasers as signal sources, numerous optical gates including optical detectors associated with memory cells, and holographic element to direct light signals to desired memory-cell locations - applied to high-capacity digital systems, supercomputers, and complex microcircuits.

Johnston, Alan R.↗

NASA NTRS1989

Internal Correction Of Errors In A DRAM

Error-correcting Hamming code built into circuit. A 256 K dynamic random-access memory (DRAM) circuit incorporates Hamming error-correcting code in its layout. Feature provides faster detection and correction of errors at less cost in amount of equipment, operating time, and software. On-chip error-correcting feature also makes new DRAM less susceptible to single-event upsets.

Zoutendyk, John A.↗

NASA NTRS1988

Sparse distributed memory prototype: Principles of operation

Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components.

Flynn, Michael J.↗

NASA NTRS1988

Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

Rogers, David↗

NASA NTRS1989

Total dose effect on soft error rate for dynamic metal-oxide-semiconductor memory cells

A simple model for the soft error rate for dynamic metal-oxide-semiconductor random access memories due to normal galactic radiation was devised and then used to calculate the rate of decrease of the single-event-upset rate with total radiation dose. The computation shows that the decrease in the soft error rate is less than 10 percent per day if the shielding is 0.5 g/sq cm and the spacecraft is in a geosynchronous orbit. The decrease is considerably less in a polar orbiting device.

Benumof, Reuben↗

NASA NTRS1990

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗

NASA NTRS1990

32-Bit-Wide Memory Tolerates Failures

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Buskirk, Glenn A.↗

NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗

NASA NTRS1989

Characterization of multiple-bit errors from single-ion tracks in integrated circuits

The spread of charge induced by an ion track in an integrated circuit and its subsequent collection at sensitive nodal junctions can cause multiple-bit errors. The authors have experimentally and analytically investigated this phenomenon using a 256-kb dynamic random-access memory (DRAM). The effects of different charge-transport mechanisms are illustrated, and two classes of ion-track multiple-bit error clusters are identified. It is demonstrated that ion tracks that hit a junction can affect the lateral spread of charge, depending on the nature of the pull-up load on the junction being hit. Ion tracks that do not hit a junction allow the nearly uninhibited lateral spread of charge.

Zoutendyk, J. A.↗

NASA NTRS1989

Telemetry data storage systems technology for the Space Station Freedom era

This paper examines the requirements and functions of the telemetry-data recording and storage systems, and the data-storage-system technology projected for the Space Station, with particular attention given to the Space Optical Disk Recorder, an on-board storage subsystem based on 160 gigabit erasable optical disk units each capable of operating at 300 M bits per second. Consideration is also given to storage systems for ground transport recording, which include systems for data capture, buffering, processing, and delivery on the ground. These can be categorized as the first in-first out storage, the fast random-access storage, and the slow access with staging. Based on projected mission manifests and data rates, the worst case requirements were developed for these three storage architecture functions. The results of the analysis are presented.

Dalton, John T.↗

NASA NTRS1991

Multiple-Bit Errors Caused By Single Ions

Report describes experimental and computer-simulation study of multiple-bit errors caused by impingement of single energetic ions on 256-Kb dynamic random-access memory (DRAM) integrated circuit. Studies illustrate effects of different mechanisms for transport of charge from ion tracks to various elements of integrated circuits. Shows multiple-bit errors occur in two different types of clusters about ion tracks causing them.

Zoutendyk, John A.↗

NASA NTRS1991

DOS Batch Files As Control Programs

Computer-programming technique circumvents maximum of 640K imposed on random-access memory (RAM) by DOS (Disk Operating System) software. Involves breaking application program into smaller programs. Each resulting subprogram, when compiled and linked, must be small enough to fit within 640K of RAM. Retrieved from storage on disk as needed. In terms of DOS software, each subprogram ".EXE" file executed in "stand-alone" manner.

Van Dyk, David A.↗

NASA NTRS1991

Neural-Network Simulator

F77NNS (FORTRAN 77 Neural Network Simulator) computer program simulates popular back-error-propagation neural network. Designed to take advantage of vectorization when used on computers having this capability, also used on any computer equipped with ANSI-77 FORTRAN Compiler. Problems involving matching of patterns or mathematical modeling of systems fit class of problems F77NNS designed to solve. Program has restart capability so neural network solved in stages suitable to user's resources and desires. Enables user to customize patterns of connections between layers of network. Size of neural network F77NNS applied to limited only by amount of random-access memory available to user.

Mitchell, Paul H.↗

NASA NTRS1991

Software for Optical Archive and Retrieval (SOAR) user's guide, version 4.2

The optical disk is an emerging technology. Because it is not a magnetic medium, it offers a number of distinct advantages over the established form of storage, advantages that make it extremely attractive. They are as follows: (1) the ability to store much more data within the same space; (2) the random access characteristics of the Write Once Read Many optical disk; (3) a much longer life than that of traditional storage media; and (4) much greater data access rate. Software for Optical Archive and Retrieval (SOAR) user's guide is presented.

Davis, Charles↗

NASA NTRS1989

Optical archiving for scientific data

Write-once-read-many (WORM) optical disk technology is now practical for use as (1) a near online storage media, (2) long-term storage in a passive repository, and (3) under some circumstances, transporting from and to data generators and data users at remote sites. Optical technology provides several significant advantages over magnetic tapes as a data storage media because it is more compact, provides random access, has a longer lifetime, at least 30 years, and is less sensitive to environmental factors such as temperature and humidity. Two major archival projects using optical technology underway are discussed: the Coastal Zone Color Scanner data and the Dynamics Explorer data. Both projects have used the software for optical archive and retrieval (SOAR) to transfer data in a volume format that can be read transparently by VAX/VMS. Through the use of this software technique, (1) data generators and data users do not have to rewrite extant software and (2) the VAX/VMS Files-11 volume format is in wide use, so it can serve as an interim standard and will be accessible in the long-term.

Lowrey, Barbara E.↗