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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 487 records · Page 27
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Design of power electronics for TVC EMA systems

The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.

Nelms, R. Mark↗
NASA NTRS1993

Design of CMOS logic gates for TID radiation

The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

Attia, John Okyere↗
NASA NTRS1994

Silicon device performance measurements to support temperature range enhancement

Silicon based power devices can be used at 200 C. The device measurements made during this program show a predictable shift in device parameters with increasing temperature. No catastrophic or abrupt changes occurred in the parameters over the temperature range. As expected, the most dramatic change was the increase in leakage currents with increasing temperature. At 200 C the leakage current was in the milliAmp range but was still several orders of magnitude lower than the on-state current capabilities of the devices under test. This increase must be considered in the design of circuits using power transistors at elevated temperature. Three circuit topologies have been prototyped using MOSFET's and IGBT's. The circuits were designed using zero current or zero voltage switching techniques to eliminate or minimize hard switching of the power transistors. These circuits have functioned properly over the temperature range. One thousand hour life data have been collected for two power supplies with no failures and no significant change in operating efficiency. While additional reliability testing should be conducted, the feasibility of designing soft switched circuits for operation at 200 C has been successfully demonstrated.

Bromstead, James↗
NASA NTRS1995

Improved L-C resonant decay technique for Q measurement of quasilinear power inductors: New results for MPP and ferrite powdered cores

The L-C resonant decay technique for measuring circuit Q or losses is improved by eliminating the switch from the inductor-capacitor loop. A MOSFET switch is used instead to momentarily connect the resonant circuit to an existing voltage source, which itself is gated off during the decay transient. Very reproducible, low duty cycle data could be taken this way over a dynamic voltage range of at least 10:1. Circuit Q is computed from a polynomial fit to the sequence of the decaying voltage maxima. This method was applied to measure the losses at 60 kHz in inductors having loose powder cores of moly permalloy and an Mn-Zn power ferrite. After the copper and capacitor losses are separated out, the resulting specific core loss is shown to be roughly as expected for the MPP powder, but anomalously high for the ferrite powder. Possible causes are mentioned.

Niedra, Janis M.↗
NASA NTRS1995

Texturing Copper To Reduce Secondary Emission Of Electrons

Ion-beam process produces clean, deeply textured surfaces on copper substrates with reduced secondary electron emission. In process, molybdenum ring target positioned above and around copper substrate. Target potential repeatedly switched on and off. Switching module described in "High-Voltage MOSFET Switching Circuit" (LEW-15986). Useful for making collector electrodes for traveling-wave-tube and klystron microwave amplifiers, in which secondary emission of electrons undesirable because of reducing efficiency.

Jensen, Kenneth A.↗
NASA NTRS1995

Low-temperature operation of a Buck DC/DC converter

Low-temperature (77 K) operation of a 42/28 V, 175 W, 50 kHz PWM Buck DC/DC converter designed with commercially available components is reported. Overall, the converter losses decreased at 77 K compared to room temperature operation. A full-load efficiency of 97 percent was recorded at liquid-nitrogen temperature, compared to 95.8 percent at room temperature. Power MOSFET operation improved significantly where as the output rectifier operation deteriorated at low-temperature. The performance of the output filter inductor and capacitor did not change significantly at 77 K compared to room temperature performance. It is possible to achieve high-density and high efficiency power conversion at low-temperatures due to improved electronic, electrical and thermal properties of materials.

Ray, Biswajit↗
NASA NTRS1996

CMOS Active-Pixel Image Sensor With Simple Floating Gates

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fossum, Eric R.↗
NASA NTRS1996

Study of a High Voltage Ion Engine Power Supply

A complete laboratory breadboard version of a ion engine power converter was built and tested. This prototype operated on a line voltage of 80-120 Vdc, and provided output ratings of 1100 V at 1.8 kW, and 250 V at 20 mA. The high-voltage (HV) output voltage rating was revised from the original value of 1350 V at the beginning of the project. The LV output was designed to hold up during a 1-A surge current lasting up to 1 second. The prototype power converter included a internal housekeeping power supply which also operated from the line input. The power consumed in housekeeping was included in the overall energy budget presented for the ion engine converter. HV and LV output voltage setpoints were commanded through potentiometers. The HV converter itself reached its highest power efficiency of slightly over 93% at low line and maximum output. This would dip below 90% at high line. The no-load (rated output voltages, zero load current) power consumption of the entire system was less than 13 W. A careful loss breakdown shows that converter losses are predominately Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) conduction losses and HV rectifier snubbing losses, with the rectifier snubbing losses becoming predominant at high line. This suggests that further improvements in power efficiency could best be obtained by either developing a rectifier that was adequately protected against voltage overshoot with less snubbing, or by developing a pre-regulator to reduced the range of line voltage on the converter. The transient testing showed the converter to be fully protected against load faults, including a direct short-circuit from the HV output to the LV output terminals. Two currents sensors were used: one to directly detect any core ratcheting on the output transformer and re-initiate a soft start, and the other to directly detect a load fault and quickly shut down the converter for load protection. The finished converter has been extensively fault tested without failure. The finished converter has been packaged suitable for use as a laboratory prototype for further testing. The finished converter is readily transportable. An article on design issues for high voltage converters for ion engines is included as an attachement.

Stuart, Thomas A.↗
NASA NTRS1998

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

Duen Ho, Fat↗
NASA NTRS2000

Analysis and Enhancement of Low-Light-Level Performance of Photodiode-Type CMOS Active Pixel Images Operated with Sub-Threshold Reset

Noise in photodiode-type CMOS active pixel sensors (APS) is primarily due to the reset (kTC) noise at the sense node, since it is difficult to implement in-pixel correlated double sampling for a 2-D array. Signal integrated on the photodiode sense node (SENSE) is calculated by measuring difference between the voltage on the column bus (COL) - before and after the reset (RST) is pulsed. Lower than kTC noise can be achieved with photodiode-type pixels by employing "softreset" technique. Soft-reset refers to resetting with both drain and gate of the n-channel reset transistor kept at the same potential, causing the sense node to be reset using sub-threshold MOSFET current. However, lowering of noise is achieved only at the expense higher image lag and low-light-level non-linearity. In this paper, we present an analysis to explain the noise behavior, show evidence of degraded performance under low-light levels, and describe new pixels that eliminate non-linearity and lag without compromising noise.

Pain, Bedabrata↗
NASA NTRS1997

Low Temperature Operation of a Switching Power Converter

The low temperature operation of a 48 W, 50 kHz, 36/12 V pulse width modulated (PWM) buck de-de power converter designed with standard commercially available components and devices is reported. The efficiency of the converter increased from 85.6% at room temperature (300 K) to 92.0% at liquid nitrogen temperature (77 K). The variation of power MOSFET, diode rectifier, and output filter inductor loss with temperature is discussed. Relevant current, voltage. and power waveforms are also included.

Anglada-Sanchez, Carlos R.↗
NASA NTRS2001

An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

Jackson, S. A.↗
NASA NTRS1997

Simulation of Ultra-Small Electronic Devices: The Classical-Quantum Transition Region

Concern is increasing about how quantum effects will impact electronic device operation as down-scaling continues along the SIA Roadmap through 2010. This document describes part of a new semiconductor device modeling (SDM) program at NAS to investigate these concerns by utilizing advanced NAS and third-party numerical computation software to rapidly implement and investigate electronic device models including quantum effects. This SDM project will investigate quantum effects in devices in the classical-quantum transition region, especially sub-0.1 mm MOSFETs. Specific tasks planned for this project include the use of quantum corrections to the classical drift-diffusion and hydrodynamic models of electron transport, arid the use of nominally quantum models including significant scattering.

Biegel, Bryan A.↗
NASA NTRS1998

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Rafferty, Connor S.↗
NASA NTRS2003

Where is scattering important in nanotransistors?

This viewgraph presentation provides an overview of scattering in nanotransistors. Topics covered include: scattering mechanisms, devices used and series resistance. The authors conclude: (1) the influence of electron-photon scattering on the on-current of dual gate MOSFET's using the non-equilibrium Green's function method and (2) the influence of the drain extension region can no longer be modeled as a series resistance.

Anantram, M. P.↗
NASA NTRS1999

Analysis of Carbon Nanotube Field-Effect-Transistors (FETs)

This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.

Yamada, Toshishige↗
NASA NTRS2002

The four-gate transistor

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

neuro-prosthetic devices cortical signals↗
NASA NTRS1993

High Efficiency Synchronous Rectification in Spacecraft

This paper examines the implementaion of MOSFETs as synchronous rectifiers which results in a substantial improvement in power processing efficency and therefore may result in significant reduction of spacecraft mass and volum for the same payload.

Spacecraft Power↗