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At least 451 records · Page 25

Programmable Ultra-Lightweight System Adaptable Radio Satellite Base Station

With the explosion of the CubeSat, small sat, and nanosat markets, the need for a robust, highly capable, yet affordable satellite base station, capable of telemetry capture and relay, is significant. The Programmable Ultra-Lightweight System Adaptable Radio (PULSAR) is NASA Marshall Space Flight Center's (MSFC's) software-defined digital radio, developed with previous Technology Investment Programs and Technology Transfer Office resources. The current PULSAR will have achieved a Technology Readiness Level-6 by the end of FY 2014. The extensibility of the PULSAR will allow it to be adapted to perform the tasks of a mobile base station capable of commanding, receiving, and processing satellite, rover, or planetary probe data streams with an appropriate antenna.

Varnavas, Kosta↗

A Programmable SDN+NFV Architecture for UAV Telemetry Monitoring

With the explosive growth in UAV numbers forecast worldwide, a core concern is how to manage the ad-hoc network configuration required for mobility management. As UAVs migrate among ground control stations, associated network services, routing and operational control must also rapidly migrate to ensure a seamless transition. In this paper, we present a novel, lightweight and modular architecture which supports high mobility, resilience and flexibility through the application of SDN and NFV principles on top of the UAV infrastructure. By combining SDN programmability and Network Function Virtualization we can achieve resilient infrastructure migration of network services, such as network monitoring and anomaly detection, coupled with migrating UAVs to enable high mobility management. Our container-based monitoring and anomaly detection Network Functions (NFs) can be tuned to specific UAV models providing operators better insight during live, high-mobility deployments. We evaluate our architecture against telemetry from over 80flights from a scientific research UAV infrastructure.

Resilience↗

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Al Hassan, Mohammad↗

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗

Self Diagnostic Accelerometer Field Programmable Gate Array (SDA FPGA)

A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) may be capable of real time or near-real time diagnostic processing to determine potential accelerometer issues during flight or other mission critical operational situations. The SDA FPGA may determine accelerometer structural health and an attachment condition using an electronics system that is smaller, more energy efficient, and more cost effective than previous diagnostic tools. Advantages of the system may include diagnosing sensors automatically, immediately, actively (i.e., confirming the fault), and consistently, without the influence of a human operator. Customizable SDA algorithms may be adjusted to the specific needs of the sensor/environment.

Tokars, Roger P.↗

One Time Programmable Antifuse Memory Based on Bulk Junctionless Transistor

One time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.

Antifuse↗

High temperature experiments using programmable transistor array

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip, which recovers functionality until 280oC. We show in this paper the functionality recovery at high temperatures for a variety of circuits, including rectifiers, amplifiers and filters.

Duong, Vu↗

Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays

This work discusses mitigation selection and qualification techniques for Xilinx reconfigurable field programmable gate arrays (FPGAs). The aim of the paper is to provide readers with a better understanding of the engineering/reliability/project cost relationship that occurs when developing a mitigation strategy for static random access memory (SRAM)-based FPGAs.

Allen, Gregory↗

An X-ray Interferometry Concept for the ESA Voyage 2050 Programme

We have proposed the development of X-ray interferometry as part of ESA’s Voyage 2050 programme, to reveal the universe at high energies with ultra-high spatial resolution. With only a 1 m baseline, which could be accommodated on a single spacecraft, X-ray interferometry can reach 100μas resolution at 10 ̊A (1.24 keV) and exceed that of the Event Horizon Telescope at 2 ̊A (6.2 keV). A multi-spacecraft ‘constellation’ interferometer would resolve well below 1μas. Here we focus on the single-spacecraft interferometer design and discuss the process of fringe detection and image reconstruction from multiple baselines, showing simulated images of testcases from our Voyage 2050 White Paper. We also discuss the challenges and feasibility of reaching the technical requirements needed for a single-spacecraft interferometer. Most key requirements are already feasible or within easy reach. Besides a ground-based testbed, covered elsewhere in these proceedings, the most important areas for development include large format, small-pixel X-ray detectors and pointing which is stable or can be reconstructed to tens of μas precision.

Phil Uttley↗

Sidelobe Reduction and Mode-Purity Enhancement of Vortex Beams from a Programmable, Rectangular Phased Array Antenna

Tapering the magnitude of the electric field excitation of a programmable, rectangular phased array has been employed to achieve sidelobe reduction and enhancement of mode purity in vortex beams, which carry non-zero orbital angular momentum. Far-field radiation patterns pertaining to a commercial-off-the-shelf, 256-element antenna were generated via electromagnetic simulation. The patterns were decomposed into weighted sums of Laguerre-Gaussian modes. The extracted coupling coefficients were used to gauge mode purity. In comparison to a uniform excitation of the phased array elements, our studies indicate that employing a tapering technique can result in a 10.7 dB reduction of sidelobe power and a 7.22 dB improvement in worst-case, mode-to-mode cross-talk.

orbital angular momentum, phased array, beamformin↗

Performance of the Dragonfly Mass Spectrometer (DraMS) Programmable UV Laser Source Engineering Test Unit (ETU)

NASA’s Dragonfly mission will sample surface materials from multiple sites on Saturn’s largest moon, Titan, in exploration of its potential for prebiotic chemistry. We report on the performance of our short-pulsed UV laser transmitter, developed for the Dragonfly’s on-board Mass Spectrometer (DraMS). Our engineering test unit (ETU) has completed flight qualification and demonstrated its operational science requirements, such that the final flight unit build can begin. The Titan Hydrocarbon Analysis Nanosecond Optical Source (THANOS) ETU laser produces 266 nm laser pulses at programmable energy levels in order to create high resolution laser desorption mass spectrometry (LDMS) measurements. The laser operates in short bursts of 1-50 pulses, each at < 2 ns pulse width, at a 100 Hz repetition rate. Creating a sealed Titanium unit, capable of operation on the extreme environment of Titan’s surface was a major engineering challenge. The laser successfully demonstrated its ability to meet all operational requirements in terms of pulse energy, beam pointing on target and repeatability even after extensive environmental testing.

Matthew W Mullin↗

Performance of the Dragonfly Mass Spectrometer (DraMS) Programmable UV Laser Source Engineering Test Unit (ETU)

NASA’s Dragonfly mission will sample surface materials from multiple sites on Saturn’s largest moon, Titan, in exploration of its potential for prebiotic chemistry. We report on the performance of our short-pulsed UV laser transmitter, developed for the Dragonfly’s on-board Mass Spectrometer (DraMS). Our engineering test unit (ETU) has completed flight qualification and demonstrated its operational science requirements, such that the final flight unit build can begin. The Titan Hydrocarbon Analysis Nanosecond Optical Source (THANOS) ETU laser produces 266 nm laser pulses at programmable energy levels in order to create high resolution laser desorption mass spectrometry (LDMS) measurements. The laser operates in short bursts of 1-50 pulses, each at < 2 ns pulse width, at a 100 Hz repetition rate. Creating a sealed Titanium unit, capable of operation on the extreme environment of Titan’s surface was a major engineering challenge. The laser successfully demonstrated its ability to meet all operational requirements in terms of pulse energy, beam pointing on target and repeatability even after extensive environmental testing.

Matthew Mullin↗

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗

Full-frame, programmable hyperspectral imager

A programmable, many-band spectral imager based on addressable spatial light modulators (ASLMs), such as micro-mirror-, micro-shutter- or liquid-crystal arrays, is described. Capable of collecting at once, without scanning, a complete two-dimensional spatial image with ASLM spectral processing applied simultaneously to the entire image, the invention employs optical assemblies wherein light from all image points is forced to impinge at the same angle onto the dispersing element, eliminating interplay between spatial position and wavelength. This is achieved, as examples, using telecentric optics to image light at the required constant angle, or with micro-optical array structures, such as micro-lens- or capillary arrays, that aim the light on a pixel-by-pixel basis. Light of a given wavelength then emerges from the disperser at the same angle for all image points, is collected at a unique location for simultaneous manipulation by the ASLM, then recombined with other wavelengths to form a final spectrally-processed image.

47 OTHER INSTRUMENTATION↗

Detecting Payload Attacks on Programmable Logic Controllers (PLCs)

Programmable logic controllers (PLCs) play critical roles in industrial control systems (ICS). Providing hardware peripherals and firmware support for control programs (i.e., a PLC’s “payload”) written in languages such as ladder logic, PLCs directly receive sensor readings and control ICS physical processes. An attacker with access to PLC development software (e.g., by compromising an engineering workstation) can modify the payload program and cause severe physical damages to the ICS. To protect critical ICS infrastructure, we propose to model runtime behaviors of legitimate PLC payload program and use runtime behavior monitoring in PLC firmware to detect payload attacks. By monitoring the I/O access patterns, network access patterns, as well as payload program timing characteristics, our proposed firmware-level detection mechanism can detect abnormal runtime behaviors of malicious PLC payload. Using our proof-of-concept implementation, we evaluate the memory and execution time overhead of implementing our proposed method and find that it is feasible to incorporate our method into existing PLC firmware. In addition, our evaluation results show that a wide variety of payload attacks can be effectively detected by our proposed approach. The proposed firmware-level payload attack detection scheme complements existing bumpin- the-wire solutions (e.g., external temporal-logic-based model checkers) in that it can detect payload attacks that violate realtime requirements of ICS operations and does not require any additional apparatus.

42 ENGINEERING↗

Automated Reconstruction of Control Logic for Programmable Logic Controller Forensics

This paper presents Similo, an automated scalable framework for control logic forensics in industrial control systems. Similo is designed to investigate denial of engineering operations (DEO) attacks, recently demonstrated to hide malicious control logic in a programmable logic controller (PLC) at field sites from an engineering software (at control center). The network traffic (if captured) contains substantial evidence to investigate DEO attacks including manipulation of control logic. Laddis, a state-of-the-art forensic approach for DEO attacks, is a binary-logic decompiler for the Allen-Bradley’s RSLogix engineering software and MicroLogix 1400 PLC. It is developed with extensive manual reverse engineering effort of the underlying proprietary network protocol and the binary control logic. Unfortunately, Laddis is not scalable and requires similar efforts to extend on other engineering software/PLCs. The proposed solution, Similo, is based on the observation that engineering software of different vendors are equipped with decompilers. Similo is a virtual-PLC framework that integrates the decompilers with their respective (previously-captured) ICS network traffic of control logic. It recovers the binary logic into a high-level source code (of the programming languages defined by IEC 61131-3 standard) automatically. Similo can work with both proprietary/open protocols without requiring protocol specifications and the binary formats of control logic. Thus, it is scalable to different ICS vendors. We evaluate Similo on three PLCs of two ICS vendors, i.e. MicroLogix 1400, MicroLogix 1100, and Modicon M221. These PLCs support proprietary protocols and the control logics written in two programming languages: Ladder Logic and Instruction List. The evaluation results show that Similo can accurately reconstruct a control logic from an ICS network traffic and can be used to investigate the DEO attacks effectively.

Ali qasim, Syed↗

Dynamic virtualized field-programmable gate array resource control for performance and reliability

A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.

97 MATHEMATICS AND COMPUTING↗