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At least 433 records · Page 24

Conceptual design and analysis of an infared horizon sensor with compensation for atmospheric variability

A horizon detection logic, based on a ratio-of-integrated-radiance concept, which detects the earth's horizon at a relatively stable height under all geographic and meteorological conditions was evaluated by computer simulation on a body of synthesized radiance profiles. An error-sensitivity analysis of the concept was performed, and optimum design parameter values for a sensor were determined. A conceptual design for an improved 15 micron sensor based on this analysis is discussed.

Jalink, A., Jr.↗

An Embedded Reconfigurable Logic Module

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

Tucker, Jerry H.↗

Flexible body control using neural networks

Progress is reported on the control of Control Structures Interaction suitcase demonstrator (a flexible structure) using neural networks and fuzzy logic. It is concluded that while control by neural nets alone (i.e., allowing the net to design a controller with no human intervention) has yielded less than optimal results, the neural net trained to emulate the existing fuzzy logic controller does produce acceptible system responses for the initial conditions examined. Also, a neural net was found to be very successful in performing the emulation step necessary for the anticipatory fuzzy controller for the CSI suitcase demonstrator. The fuzzy neural hybrid, which exhibits good robustness and noise rejection properties, shows promise as a controller for practical flexible systems, and should be further evaluated.

Mccullough, Claire L.↗

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Fura, David A.↗

Improved On-Chip Measurement of Delay in an FPGA or ASIC

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chen, Yuan↗

Inner loop flight control for the High-Speed Civil Transport

High-speed aerospace vehicles which employ high strength, light weight, yet deformable materials may exhibit significant interaction between the rigid-body and vibrational dynamics. Preliminary High-Speed Civil Transport (HSCT) configurations are a prime example. Traditionally, separate control systems have been used to augment the rigid-body and vibrational dynamics. In the HSCT arena, the highly coupled motions may not allow this design freedom. The research activity addresses two specific issues associated with the design and development of an integrated flight control system (FCS) for HSCT configurations, which are discussed next. The HSCT is expected to have a short period instability at subsonic speeds. Flight vehicles with this characteristic (i.e., F-16, F-22, X-29, Space Shuttle) are stabilized with what is called a superaugmented pitch rate loop. One concern is 'Will this stability augmentation logic work for a HSCT?' Studies show that an idealized pitch rate design would be acceptable, but is not realistic. Investigations using a contaminated pitch rate design reveal serious hurdles to overcome in the FCS design. Mounting location for the pitch rate sensor is critical. Results indicate a forward location leads to destabilizing pick-up of aeroelastic modes, while aft locations lead to undesirable coupling of the dominate pitch mode with the first aeroelastic mode. Intermediate locations for the sensor may not be acceptable. The source of the problem is the presence of low frequency aeroelastic modes in HSCT configurations, which are not present in vehicles currently using the superaugmented logic. To say the least, a conventional superaugmented pitch rate loop strategy may have undesirable characteristics. An unconventional strategy, which attempts to eliminate the above deficiencies by blending several pitch rate signals, indicates an improvement in the FCS architecture feasibility, but is still lacking in some respects. The HSCT configuration does not have aerodynamic surfaces in the vicinity of the nose (i.e., no canard or vane). A second concern is 'Can the fuselage bending/torsion aeroelastic modes be effectively augmented without sufficient control input near the vehicle nose?' The superaugmented FCS results above may be suggesting the necessity of a secondary feedback loop to achieve an acceptable integrated FCS. Preliminary analysis of HSCT aeroelastic mode shapes indicate the use of existing wing leading edge devices as a second control input may be lacking in control authority for the rigid-body attitude and aeroelastic modes. An effort is underway to incorporate generic wing leading edge devices and canards into a generic HSCT model for the purpose of assessing additional control authority and it's use in candidate FCS designs. A generic HSCT mathematical model was necessary for the studies above. A HSCT category model is available in NASA-CR-172201. This model describes the linear, longitudinal dynamics about the following flight condition: ascent, W = 730,000 lbs, h = 6,500 ft, M = 0.6. The model incorporates the full rigid-body variable set, as well as eighteen aeroelastic modes. Elevator deflection serves as the control input. Modifications to the model include the incorporation of relaxed static stability (i.e., static margin from -7.3% to +10%) and additional control inputs.

Newman, Brett A.↗

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗

Digital controllers for VTOL aircraft

Using linear-optimal estimation and control techniques, digital-adaptive control laws have been designed for a tandem-rotor helicopter which is equipped for fully automatic flight in terminal area operations. Two distinct discrete-time control laws are designed to interface with velocity-command and attitude-command guidance logic, and each incorporates proportional-integral compensation for non-zero-set-point regulation, as well as reduced-order Kalman filters for sensor blending and noise rejection. Adaptation to flight condition is achieved with a novel gain-scheduling method based on correlation and regression analysis. The linear-optimal design approach is found to be a valuable tool in the development of practical multivariable control laws for vehicles which evidence significant coupling and insufficient natural stability.

Stengel, R. F.↗

A bit serial sequential circuit

Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.

Hu, S.↗

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗

Three-dimensional flow in radial turbomachinery and its impact on design

In the two papers on the 'Theory of Blade Design for Large Deflections' published in 1984, a new inverse design technique was presented for designing the shape of turbomachinery blades in three-dimensional flow. The technique involves the determination of the blade profile from the specification of a distribution of the product of the radius and the pitched averaged tangential velocity (i.e., r bar-V(sub theta), the mean swirl schedule) within the bladed region. This is in contrast to the conventional inverse design technique for turbomachinery blading in two dimensional flow in which the blade surface pressure or velocity distribution is specified and the blade profile determined as a result; this is feasible in two-dimensional flow because the streamlines along the blade surfaces are known a priori. However, in three-dimensional flow, the stream surface is free to deform within the blade passage so that the streamlines on the blade surfaces are not known a priori; thus it is difficult and not so useful to prescribe the blade surface pressure or velocity distribution and determine the resulting blade profile. It therefore seems logical to prescribe the swirl schedule within the bladed region for designing a turbomachinery blade profile in three-dimensional flow. Furthermore, specifying r bar-V(sub theta) has the following advantages: (1) it is related to the circulation around the blade (i.e., it is an aerodynamic quantity); (2) the work done or extracted is approximately proportional to the overall change in r bar-V(sub theta) across a given blade row (Euler turbine equation); and (3) the rate of change of r bar-V(sub theta) along the mean streamline at the blade is related to the pressure jump across the blade and therefore the blade loading. Since the publications of those two papers, the technique has been applied to the design of a low speed as well as a high speed radial inflow turbine (for turbocharger applications) both of which showed definite improvements in performance over that of wheels of conventional designs, the design study of a high pressure ratio radial inflow turbine with and without splitter blades.

Tan, Choon S.↗

SOLON: An autonomous vehicle mission planner

The State-Operator Logic Machine (SOLON) Planner provides an architecture for effective real-time planning and replanning for an autonomous vehicle. The highlights of the system, which distinguish it from other AI-based planners that have been designed previously, are its hybrid application of state-driven control architecture and the use of both schematic representations and logic programming for the management of its knowledge base. SOLON is designed to provide multiple levels of planning for a single autonomous vehicle which is supplied with a skeletal, partially-specified mission plan at the outset of the vehicle's operations. This mission plan consists of a set of objectives, each of which will be decomposable by the planner into tasks. These tasks are themselves comparatively complex sets of actions which are executable by a conventional real-time control system which does not perform planning but which is capable of making adjustments or modifications to the provided tasks according to constraints and tolerances provided by the Planner. The current implementation of the SOLON is in the form of a real-time simulation of the Planner module of an Intelligent Vehicle Controller (IVC) on-board an autonomous underwater vehicle (AUV). The simulation is embedded within a larger simulator environment known as ICDS (Intelligent Controller Development System) operating on a Symbolics 3645/75 computer.

Dudziak, M. J.↗

Theorem Proving in Intel Hardware Design

For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

O'Leary, John↗

The OGO attitude control subsystem redesign as a result of OGO 3 experience. Volume 1: System analysis and design studies

An oscillation in the OGO-3 roll control channel, resulting from the EP-5 and EP-6 boom motion coupling into the control channel and causing loss of attitude control, is investigated. The study includes (1) an analysis of the OGO-3 and OGO-2 flight data to determine the nature and extent of the roll oscillation phenomena, (2) design analysis of the complete attitude control subsystem (ACS) to evolve changes which would prevent recurrences of the coupled ACS boom oscillation observed on OGO-3, and (3) analog simulations to verify the performance of the design changes selected. Portions of OGO-3 and OGO-2 flight data are illustrated and the major flexible body oscillation are identified. A model of the major flexible appendage dynamics is developed and is shown analytically and through analog simulations to reproduce the OGO-3 oscillation phenomena. The design changes which were found necessary are: a reversal delay logic for the roll reaction wheels, widening of the solar array dead zone from 0.5 to 1.0 deg, and modification of the OPEP control loop to include a filter and stabilizing feedback loops.

Mckenna, K. J.↗

Advanced Power Conditioning System

The second portion of the advanced power conditioning system development program is reported. Five 100-watt parallel power stages with majority-vote-logic feedback-regulator were breadboarded and tested to the design goals. The input voltage range was 22.1 to 57.4 volts at loads from zero to 500 watts. The maximum input ripple current was 200 mA pk-pk (not including spikes) at 511 watts load; the output voltage was 56V dc with a maximum change of 0.89 volts for all variations of line, load, and temperature; the maximum output ripple was 320 mV pk-pk at 512 watts load (dependent on filter capacitance value); the maximum efficiency was 93.9% at 212 watts and 50V dc input; the minimum efficiency was 87.2% at 80-watt load and 50V dc input; the efficiency was above 90% from 102 watts to 372 watts; the maximum excursion for an 80-watt load change was 2.1 volts with a recovery time of 7 milliseconds; and the unit performed within regulation limits from -20 C to +85 C. During the test sequence, margin tests and failure mode tests were run with no resulting degradation in performance.

Johnson, N. L.↗

MSFC crack growth analysis computer program, version 2 (users manual)

An updated version of the George C. Marshall Space Flight Center Crack Growth Analysis Program is described. The updated computer program has significantly expanded capabilities over the original one. This increased capability includes an extensive expansion of the library of stress intensity factors, plotting capability, increased design iteration capability, and the capability of performing proof test logic analysis. The technical approaches used within the computer program are presented, and the input and output formats and options are described. Details of the stress intensity equations, example data, and example problems are presented.

Creager, M.↗

Automated maneuvering decisions for air-to-air combat

A game-matrix approach is used to generate intelligent maneuvering decisions for nap-of-the-earth one-on-one helicopter air combat over hilly terrain. Decisions are made in real time using the AUTOMAN program by comparing scores based upon the predicted orientation, range, velocity, and terrain clearance for various maneuver combinations of both aircraft. The program has been demonstrated at the NASA Ames Vertical Motion Simulator, providing manned helicopter simulations. Sample trajectories from a stand-alone version of the program designed for nonpiloted simulations demonstrate that the present automated maneuvering logic generates some of the tactics employed by experienced pilots in flight tests. The program also has application to fixed-wing aircraft simulations.

Austin, Fred↗