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At least 415 records · Page 23

Rendezvous algorithms for large-scale modeling and simulation

Rendezvous algorithms encode a communication pattern that is useful when processors sending data do not know who the receiving processors should be, or vice versa. The idea is to define an intermediate decomposition where datums from different sending processors can ”rendezvous” to perform a computation, in a manner that both the senders and eventual receivers of the results can identify the appropriate rendezvous processor. Though they were originally designed for interpolating between overlaid grids with independent parallel decompositions (Plimpton et al., 2004), we have recently found rendezvous algorithms useful for a variety of operations in particle- or grid-based simulation codes when running large problems on large numbers of processors. In particular, we show they can perform well when a load-balanced intermediate decomposition is randomized and not spatial, requiring all-to-all communication to move data between processors. In this case rendezvous algorithms leverage the large bisection communication bandwidths which parallel machines provide. We describe how rendezvous algorithms work in a scientific computing context and give specific examples for molecular dynamics and Direct Simulation Monte Carlo codes which result in dramatic performance improvements versus simpler algorithms which do not scale as well. We explain how a generic rendezvous algorithm can be implemented, and also point out similarities with the MapReduce paradigm popularized by Google and Hadoop.

97 MATHEMATICS AND COMPUTING↗

Dynamic load balance scheme for the DSMC algorithm

The direct simulation Monte Carlo (DSMC) algorithm, devised by Bird, has been used over a wide range of various rarified flow problems in the past 40 years. While the DSMC is suitable for the parallel implementation on powerful multi-processor architecture, it also introduces a large load imbalance across the processor array, even for small examples. The load imposed on a processor by a DSMC calculation is determined to a large extent by the total of simulator particles upon it. Since most flows are impulsively started with initial distribution of particles which is surely quite different from the steady state, the total of simulator particles will change dramatically. The load balance based upon an initial distribution of particles will break down as the steady state of flow is reached. The load imbalance and huge computational cost of DSMC has limited its application to rarefied or simple transitional flows. In this paper, by taking advantage of METIS, a software for partitioning unstructured graphs, and taking the total of simulator particles in each cell as a weight information, the repartitioning based upon the principle that each processor handles approximately the equal total of simulator particles has been achieved. The computation must pause several times to renew the total of simulator particles in each processor and repartition the whole domain again. Thus the load balance across the processors array holds in the duration of computation. The parallel efficiency can be improved effectively. The benchmark solution of a cylinder submerged in hypersonic flow has been simulated numerically. Besides, hypersonic flow past around a complex wing-body configuration has also been simulated. The results have displayed that, for both of cases, the computational time can be reduced by about 50%.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Adaptive linear predictor FIR filter based on the Cyclone V FPGA with HPS to reduce narrow band RFI in AERA radio detection of cosmic rays

We present the new approach to a filtering of radio frequency interferences (RFI) in the Auger Engineering Radio Array (AERA) which study the electromagnetic part of the Extensive Air Showers. The radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes frequency band from 30 to 80 MHz. This range is highly contaminated by human-made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. The first kind of filter used by AERA was the Median one, based on the Fast Fourier Transform (FFT) technique. The second one, which is currently in use, is the infinite impulse response (IIR) notch filter. The proposed new filter is a finite impulse response (FIR) filter based on a linear prediction (LP). A periodic contamination hidden in a registered signal (digitized in the ADC) can be extracted and next subtracted to make signal cleaner. The FIR filter requires a calculation of n=32, 64 or even 128 coefficients (dependent on a required speed or accuracy) by solving of n linear equations with coefficients built from the covariance Toeplitz matrix. This matrix can be solved by the Levinson recursion, which is much faster than the Gauss procedure. The filter has been already tested in the real AERA radio stations on Argentinean pampas with a very successful results. The linear equations were solved either in the virtual soft-core NIOSR processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. The NIOS processor is relatively slow (50 MHz internal clock), calculations performed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Test showed a very good efficiency of the RFI suppression for stationary (long-term) contaminations. However, we observed a short-time contaminations, which could not be suppressed either by the IIR-notch filter or by the FIR filter based on the linear predictions. For the LP FIR filter the refreshment time of the filter coefficients was to long and filter did not keep up with the changes of a contamination structure, mainly due to a long calculation time in a slow processors. We propose to use the Cyclone V SE chip with embedded micro-controller operating with 925 MHz internal clock to significantly reduce a refreshment time of the FIR coefficients. The lab results are promising. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Virtual Neuron: A Neuromorphic Approach for Encoding Numbers

Neuromorphic computers perform computations by emulating the human brain and are expected to be indispensable for energy-efficient computing in the future. They are primarily used in spiking neural network-based machine learning applications. However, neuromorphic computers are unable to preprocess data for these applications. Currently, data is preprocessed on a CPU or a GPU-this incurs a significant cost of transferring data from the CPU/GPU to the neuromorphic processor and vice versa. This cost can be avoided if preprocessing is done on the neuromorphic processor. To efficiently preprocess data on a neuromorphic processor, we first need an efficient mechanism for encoding data that can lend itself to all general-purpose preprocessing operations. Current encoding approaches have limited applicability and may not be suitable for all preprocessing operations. In this paper, we present the virtual neuron as a mechanism for encoding integers and rational numbers on neuromorphic processors. We evaluate the performance of the virtual neuron on physical and simulated neuromorphic hardware and show that it can perform an addition operation using 23 nJ of energy on average using a mixed-signal, memristor-based neuromorphic processor. The virtual neuron encoding approach is the first step in preprocessing data on a neuromorphic processor.

Date, Prasanna↗

PQML: Enabling the Predictive Reproducibility on NISQ Machines for Quantum ML Applications

Quantum computing represents a groundbreaking approach to high-performance computing. In recent years, quantum computers have progressed from single-qubit processors to systems boasting over 400 qubits. The presence of such a large number of qubits offers significant advantages, including enhanced computational speed—a capability beyond classical computing methods. However, the current stage of quantum computing is referred to as the noisy intermediate-scale quantum (NISQ) era. The existence of noise in this era presents challenges in testing quantum computing applications, leading to considerable variance in application results. Furthermore, the diverse noise characteristics observed across different machines exacerbate this issue, complicating the selection of the appropriate machine for application execution. In response to these challenges, we introduce our Predictive Quantum Machine Learning (PQML) tool. This tool is designed to predict outcomes when executing identical quantum machine learning applications—specifically, a critical suite of variational quantum algorithms—across various quantum computers during the NISQ era. This effort relies on data collected over a 12-month period. To the best of our knowledge, this study represents the first attempt to ensure reproducibility across quantum computers for complex circuits. Additionally, we have developed a model capable of forecasting the accuracy of quantum computers for variational quantum algorithms, with a particular emphasis on quantum machine learning as a case study.

Senapati, Priyabrata [Kent State University]↗

Multiplexer System for the SPEAR3 Booster BPM Upgrade

BPM measurements in booster synchrotrons are often only critical during accelerator commissioning or when a problem occurs. As a result, many facilities do not make large investments in booster BPM signal processors; they either have very few BPMs and/or use older generation processors. The SPEAR3 booster BPM processor system, for instance, has operated since 1990 with commercial multiplexers to switch between BPM button signals into a single dated analog BPM processor that was developed at SLAC*. This system has reached its end-of-life so we are in the process of upgrading to modern multiplexers that feed a pair of turn-by-turn Libera SPARK-ERXR processors. This low-cost solution gives us the ability to arbitrarily multiplex between BPM signals during the energy ramp with modern BPM processors. The system can either measure 2 BPMs turn-by-turn in parallel during the entire energy ramp, or sequentially measure all BPMs (2 at a time) at different time slices within the ramp. Here we show measurements of the MiniCircuits switch we chose as well as our architecture for the upgrade.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Summary of Documentation for DYNA3D-ParaDyn's Software Quality Assurance Regression Test Problems

The Software Quality Assurance (SQA) regression test suite for DYNA3D (Zywicz and Lin, 2015) and ParaDyn (DeGroot, et al., 2015) currently contains approximately 600 problems divided into 21 suites, and is a required component of ParaDyn’s SQA plan (Ferencz and Oliver, 2013). The regression suite allows developers to ensure that software modifications do not unintentionally alter the code response. The entire regression suite is run prior to permanently incorporating any software modification or addition. When code modifications alter test problem results, the specific cause must be determined and fully understood before the software changes and revised test answers can be incorporated. The regression suite is executed on LLNL platforms using a Python script and an associated data file. The user specifies the DYNA3D or ParaDyn executable, number of processors to use, test problems to run, and other options to the script. The data file details how each problem and its answer extraction scripts are executed. For each problem in the regression suite there exists an input deck, an eight-processor partition file, an answer file, and various extraction scripts. These scripts assemble a temporary answer file in a specific format from the simulation results. The temporary and stored answer files are compared to a specific level of numerical precision, and when differences are detected the test problem is flagged as failed. Presently, numerical results are stored and compared to 16 digits. At this accuracy level different processor types, compilers, number of partitions, etc. impact the results to various degrees. Thus, for consistency purposes the regression suite is run with ParaDyn using 8 processors on machines with a specific processor type (currently the Intel Xeon E5530 processor). For non-parallel regression problems, i.e., the two XFEM problems, DYNA3D is used instead. When environments or platforms change, executables using the current source code and the new resource are created and the regression suite is run. If differences in answers arise, the new answers are retained provided that the differences are inconsequential. This bootstrap approach allows the test suite answers to evolve in a controlled manner with a high level of confidence. Developers also run the entire regression suite with (serial) DYNA3D. While these results normally differ from the stored (parallel) answers, abnormal termination or wildly different values are strong indicators of potential issues.

42 ENGINEERING↗

ECP ST Capability Assessment Report (CAR) for VTK-m (FY20)

The ECP/VTK-m project is providing the core capabilities to perform scientific visualization on Exascale architectures. The ECP/VTK-m project fills the critical feature gap of performing visualization and analysis on processors like graphics-based processors. The results of this project will be delivered in tools like ParaView, Vislt, and Ascent as well as in stand-alone form. Moreover, these projects are depending on this ECP effort to be able to make effective use of ECP architectures. One of the biggest recent changes in high-performance computing is the increasing use of accelerators. Accelerators contain processing cores that independently are inferior to a core in a typical CPU, but these cores are replicated and grouped such that their aggregate execution provides a very high computation rate at a much lower power. Current and future CPU processors also require much more explicit parallelism. Each successive version of the hardware packs more cores into each processor, and technologies like hyper threading and vector operations require even more parallel processing to leverage each core's full potential. VTK-m is a toolkit of scientific visualization algorithms for emerging processor architectures. VTK-m supports the fine-grained concurrency for data analysis and visualization algorithms required to drive extreme scale computing by providing abstract models for data and execution that can be applied to a variety of algorithms across many different processor architectures. The ECP/VTK-m project is building up the VTK-m codebase with the necessary visualization algorithm implementations that run across the varied hardware platforms to be leveraged at the Exascale. We will be working with other ECP projects, such as ALPINE, to integrate the new VTK-m code into production software to enable visualization on our HPC systems.

97 MATHEMATICS AND COMPUTING↗

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

97 MATHEMATICS AND COMPUTING↗

On-package multiprocessor ground-referenced single-ended interconnect

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Dally, William J.↗

Data shuffling with hierarchical tuple spaces

Methods and systems for shuffling data are described. A processor may generate pair data from source data. The processor may insert the pair data into local tuple spaces. In response to a request for a particular key, the processor may determine a presence of the requested key in a global tuple space. The processor may, in response to a presence of the requested key in the global tuple space, update the global tuple space. The update may be based on the pair data among the local tuple spaces including the existing key. The processor may, in response to an absence of the requested key in the global tuple space, insert pair data including the missing key from the local tuple spaces into the global tuple space. The processor may fetch the requested pair data, and may shuffle the fetched data to generate a dataset.

Andrade Costa, Carlos Henrique↗

Optimization control technology for building energy conservation

A simulation processor generates and stores a simulation model based on conditions associated with a physical structure, such as a building. A neural network processor implements a neural network, having an input layer coupled to receive sensor data from the structure and having an output layer coupled to supply control signals to the at least one electrically operable environmental control device. The neural network is trained using the simulation model. A particle swarm optimization processor programmed to receive the simulation results and perform particle swarm optimization, ascertains optimal parameters for controlling the at least one electrically operable environmental control device and supplies these optimal parameters to the neural network processor. The neural network processor uses the optimal parameters supplied by the particle swarm optimization processor to further train the neural network.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Parallel 3-D method of characteristics in MPACT

A new parallel 3-D MOC kernel has been developed and implemented in MPACT which makes use of the modular ray tracing technique to reduce computational requirements and to facilitate parallel decomposition. The parallel model makes use of both distributed and shared memory parallelism which are implemented with the MPI and OpenMP standards, respectively. The kernel is capable of parallel decomposition of problems in space, angle, and by characteristic rays up to 0(104) processors. Initial verification of the parallel 3-D MOC kernel was performed using the Takeda 3-D transport benchmark problems. The eigenvalues computed by MPACT are within the statistical uncertainty of the benchmark reference and agree well with the averages of other participants. The MPACT k{sub eff} differs from the benchmark results for rodded and un-rodded cases by 11 and -40 pcm, respectively. The calculations were performed for various numbers of processors and parallel decompositions up to 15625 processors; all producing the same result at convergence. The parallel efficiency of the worst case was 60%, while very good efficiency (>95%) was observed for cases using 500 processors. The overall run time for the 500 processor case was 231 seconds and 19 seconds for the case with 15625 processors. Ongoing work is focused on developing theoretical performance models and the implementation of acceleration techniques to minimize the number of iterations to converge. (authors)

97 MATHEMATICS AND COMPUTING↗

Scalable load balancing for massively parallel distributed Monte Carlo particle transport

In order to run computer simulations efficiently on massively parallel computers with hundreds of thousands or millions of processors, care must be taken that the calculation is load balanced across the processors. Examining the workload of every processor leads to an unscalable algorithm, with run time at least as large as O(N), where N is the number of processors. We present a scalable load balancing algorithm, with run time 0(log(N)), that involves iterated processor-pair-wise balancing steps, ultimately leading to a globally balanced workload. We demonstrate scalability of the algorithm up to 2 million processors on the Sequoia supercomputer at Lawrence Livermore National Laboratory. (authors)

97 MATHEMATICS AND COMPUTING↗

Multi-node and Multi-core Performance Studies of a Monte Carlo code RMC

Over the past 15 years the architecture of high-performance computing systems has become increasingly heterogeneous with individual computing cores being subdivided into nodes and even auxiliary co-processing units such as graphics processing units or the Intel many integrated core co-processors. In fact, future computer platforms is moving toward a larger number of nodes and cores with lower memory available per node. Today, several production Monte Carlo codes use some types of hybrid parallelism strategy that makes use of shared-memory parallelism within a computing node and message-passing parallelism between nodes, which enables the codes to utilize available computing resources as much as possible, both among and within computing nodes on a cluster. The so-called hybrid parallelization is also possible with Reactor Monte Carlo Code RMC by activating both MPI and OpenMP parallel algorithms together. On HPC' which typically consists of several or several-ten thousand nodes equipping 16-32 computing intra-cores per node, simulation of RMC can be carried out in the hybrid parallelization with the MPI inter-node parallelization and the OpenMP intra-node parallelization. RMC has adopted a hybrid message-passing and shared-memory approach to parallelism, which enables the code to utilize available computing resources, both among and within computing nodes on a cluster. Shared-memory parallelism is especially valuable for large-model simulations because it enables multiple compute cores within a node to share common model information such as the geometry description, material, cross section and tally data, thus reducing the memory usage per processor. The calculation on the Tianhe-2 supercomputer took 6144 cores, resulting in a rate of 173,314,000 neutrons/minute for BEAVRS benchmark. While pin-wise full core H-M benchmark burnup calculations with millions of depletion regions was selected using MPI/OpenMP parallelism, the speed of 6,144 cores reach 1,843,200 burnable regions per minute. Keeping up with the continuing trend for increases in the number of computing resources within modern HPC systems is a significant challenge for teams that develop and maintain high-performance MC radiation transport solvers. order to address this challenge, RMC has adopted a hybrid message-passing and shared-memory approach to parallelism, which enables the code to utilize available computing resources, both among and within computing nodes on a cluster. Shared-memory parallelism is especially valuable for large-model simulations because it enables multiple compute cores within a node to share common model information such as the geometry description, material and composition definitions, and cross section data, thus reducing the memory usage per processor. The parallel performance has been studied by using two complex and representative benchmarks, H-M and BEAVRS benchmark. All simulations were run on Intel Xeon E5-2692 12 core, 2.2 GHz processors at MilkyWay-2 Super Computer with up to 12,288 available computing cores. While employing MPI parallelism, excellent parallel efficiency is achieved even above 12,000 processors and RMC reaches the parallel efficiency of 96% on 12,288 cores for the pin-by-pin computation of the BEAVRS benchmark. While BEAVRS criticality benchmark was selected using MPI/OpenMP parallelism, the speed of 6,144 cores reach 173,314,000 particles per minute. While pin-wise full core H-M benchmark burnup calculations with millions of depletion regions was selected using MPI/OpenMP parallelism, the speed of 6,144 cores reach 1,843,200 burnable regions per minute. Results from these studies demonstrate that RMC, using the hybrid parallel model described in this paper, is able to handle pin-wise full core burnup calculations with millions of depletion regions and scales well through thousands of processors. (authors)

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

CTF Parallel Performance Improvements

CTF is a modernized version of COBRA-TF (Coolant Boiling in Rod Arrays-Two Fluid), which is a thermal hydraulic (T/H) sub-channel code based on a two-phase, two-fluid model that formulates the conservation equations of mass, energy, and momentum for three fields of vapor, continuous liquid, and entrained liquid droplets. Under the Consortium for Advanced Simulation of Light Water Reactors (CASL) program sponsored by the U.S. Department of Energy, CTF is being further developed and improved for modeling and simulation of light water reactors. The code improvements for predicting T/H responses of pressurized water reactor (PWR) cores are focused on its applications to specific challenge problems deemed significant to the industry, such as departure from nucleate boiling (DNB) and crud-induced power shift. The code is also being used for T/H feedback in normal operating condition depletions in PWR and boiling water reactor designs in the reactor core simulator, Virtual Environment for Reactor Applications Core Simulator (VERA-CS), being developed by CASL. CTF modifications under the CASL program include software optimization, new closure models, and parallelization for modeling full reactor core T/H responses. The purpose of this work was to improve the parallel performance of CTF. CTF was originally parallelized via a domain-decomposition strategy using the Message Passing Interface (MPI), in which the basis of a solution domain was a physical assembly in the model. In other words, a user who wanted to perform a parallel solution with CTF had to provide the code one processor per assembly in the model (e.g., 56 cores for a 56 assembly quarter-core model, or 193 cores for a 193 assembly full-core model). This design was rigid, demanding a very specific number of processors for a model; furthermore, when CTF was run in VERA-CS-which typically uses thousands of processors- many processors sat idle during the CTF solve because CTF was unable to use any more processors than there are physical assemblies. This was not necessarily a problem if the CTF execution speed was very fast, but the average time spent in a CTF solve for prototypical PWR operating conditions was significant (i.e., over 20 % of the simulation wall time was being spent in CTF for a standard core depletion simulation). Larger, more computationally intensive simulations performed in support of the CASL DNB challenge problem demonstrated a need for improvements in this original parallelization approach. The specific goal of this work was to allow CTF to use more processors than there are physical assemblies in the model, which would not only speed up CTF and improve the overall efficiency of VERA-CS but also give users more-flexible options for executing their simulations. (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

Multi-fault Tolerance for Cartesian Data Distributions

Faults are expected to play an increasingly important role in how algorithms and applications are designed to run on future extreme-scale sys- tems. Algorithm-based fault tolerance (ABFT) is a promising approach that involves modications to the algorithm to recover from faults with lower over- heads than replicated storage and a signicant reduction in lost work compared to checkpoint-restart techniques. Fault-tolerant linear algebra (FTLA) algo- rithms employ additional processors that store parities along the dimensions of a matrix to tolerate multiple, simultaneous faults. Existing approaches as- sume regular data distributions (blocked or block-cyclic) with the failures of each data block being independent. To match the characteristics of failures on parallel computers, we extend these approaches to mapping parity blocks in several important ways. First, we handle parity computation for generalized Cartesian data distributions with each processor holding arbitrary subsets of blocks in a Cartesian-distributed array. Second, techniques to handle corre- lated failures, i.e., multiple processors that can be expected to fail together, are presented. Third, we handle the colocation of parity blocks with the data blocks and do not require them to be on additional processors. Several al- ternative approaches, based on graph matching, are presented that attempt to balance the memory overhead on processors while guaranteeing the same fault tolerance properties as existing approaches that assume independent fail- ures on regular blocked data distributions. The evaluation of these algorithms demonstrates that the additional desirable properties are provided by the pro- posed approach with minimal overhead.

Ali, Nawab↗

Measuring the capabilities of quantum computers

Quantum computers can now run interesting programs, but each processor’s capability—the set of programs that it can run successfully—is limited by hardware errors. These errors can be complicated, making it difficult to accurately predict a processor’s capability. Benchmarks can be used to measure capability directly, but current benchmarks have limited flexibility and scale poorly to many-qubit processors. We show how to construct scalable, efficiently verifiable benchmarks based on any program by using a technique that we call circuit mirroring. With it, we construct two flexible, scalable volumetric benchmarks based on randomized and periodically ordered programs. We use these benchmarks to map out the capabilities of twelve publicly available processors, and to measure the impact of program structure on each one. We find that standard error metrics are poor predictors of whether a program will run successfully on today’s hardware, and that current processors vary widely in their sensitivity to program structure.

97 MATHEMATICS AND COMPUTING↗