LEC GaAs for integrated circuit applications
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Kirkpatrick, C. G.↗
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Processing of Image Data by Integrated Circuits
Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.
Armstrong, R. W.↗
Latchup in CMOS Integrated Circuits
Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.
Soliman, K. A.↗
Test structures for propagation delay measurements on high-speed integrated circuits
The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.
Long, S. I.↗
APS-Workshop on Characterization of MMIC (Monolithic Microwave Integrated Circuit) Devices for Array Antenna
The IEEE AP-S ADCOM is attempting to expand its educational, tutorial and information exchange activities as a further benefit to all members. To this end, ADCOM will be forming specialized workshops on topics of interest to its members. The first such workshop on Characterization and Packaging of MMIC Devices for Array Antennas was conceived. The workshop took place on June 13, 1986 as part of the 1986 International Symposium sponsored by IEEE AP-S and URSI in Philadelphia, PA, June 9-13, 1986. The workshop was formed to foster the interchange of ideas among MMIC device users and to provide a forum to collect and focus information among engineers experienced and interested in the topic. After brief presentations by the panelists and comments from attendees on several subtopics, the group was divided into working committees. Each committee evaluated and made recommendations on one of the subtopics.
Smetana, Jerry↗
Single event upset immune integrated circuits for Project Galileo
Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.
Giddings, A. E.↗
Inverted thermal conversion - GaAs, a new alternative material for integrated circuits
A new type of GaAs is developed which exhibits inverted thermal conversion (ITC); i.e., it converts from conducting to semiinsulating upon annealing at about 850 C. In device fabrication, its low resistivity prior to high-temperature processing differentiates ITC GaAs from the standard semiinsulating GaAs. The ITC characteristics are obtained through control of the concentration of the midgap donor EL2 based on heat treatment and crystal-growth modification. Thus EL2 does not exist in the conducting state of ITC GaAs. Conversion to the semiinsulating state during 850 C annealing is caused by the formation of EL2.
Lagowski, J.↗
Integrated Circuit For Simulation Of Neural Network
Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.
Thakoor, Anilkumar P.↗
Addressable Inverter Matrix Tests Integrated-Circuit Wafer
Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.
Buehler, Martin G.↗
RF Testing Of Microwave Integrated Circuits
Fixtures and techniques are undergoing development. Four test fixtures and two advanced techniques developed in continuing efforts to improve RF characterization of MMIC's. Finline/waveguide test fixture developed to test submodules of 30-GHz monolithic receiver. Universal commercially-manufactured coaxial test fixture modified to enable characterization of various microwave solid-state devices in frequency range of 26.5 to 40 GHz. Probe/waveguide fixture is compact, simple, and designed for non destructive testing of large number of MMIC's. Nondestructive-testing fixture includes cosine-tapered ridge, to match impedance wavequide to microstrip. Advanced technique is microwave-wafer probing. Second advanced technique is electro-optical sampling.
Romanofsky, R. R.↗
Protective Socket For Integrated Circuits
Socket for intergrated circuits (IC's) protects from excessive voltages and currents or from application of voltages and currents in wrong sequence during insertion or removal. Contains built-in switch that opens as IC removed, disconnecting leads from signals and power. Also protects other components on circuit board from transients produced by insertion and removal of IC. Makes unnecessary to turn off power to entire circuit board so other circuits on board continue to function.
Wilkinson, Chris↗
Hall-Effect Current Sensors For Integrated Circuits
Built-in devices measure direct or alternating currents. Hall-effect sensors placed near constriction in conductor strip. Differential configuration reduces effects of stray magnetic fields, nonlinearities, and changes in temperature. Preliminary design studies and experiments with macroscopic commercial Hall-effect sensors conducted to assess feasibility, limitations, and need for further research and development of this concept. Potential applications include programmable power supplies and protective circuitry.
Rippel, Wally E.↗
Analog MOS integrated circuits
The goal was to design single-chip lowpass filters with constant group delay in the pass band and 60 dB minimum attenuation in the stop band. The desired 3 dB frequencies are (in Hertz) 2.5, 5, 10, 20, 40, 80, 160, and 320. A filter class that satisfies the constant delay (linear phase) requirement while providing quite a narrow transition band is the Bessel-Chebyshev filters. It was found that the 7th order Bessel-Chebyshev response satisfied the requirement of the filter.
Temes, Gabor C.↗
Universal test fixture for monolithic mm-wave integrated circuits calibrated with an augmented TRD algorithm
The design and evaluation of a novel fixturing technique for characterizing millimeter wave solid state devices is presented. The technique utilizes a cosine-tapered ridge guide fixture and a one-tier de-embedding procedure to produce accurate and repeatable device level data. Advanced features of this technique include nondestructive testing, full waveguide bandwidth operation, universality of application, and rapid, yet repeatable, chip-level characterization. In addition, only one set of calibration standards is required regardless of the device geometry.
Romanofsky, Robert R.↗
Lateral charge transport from heavy-ion tracks in integrated circuit chips
A 256K DRAM has been used to study the lateral transport of charge (electron-hole pairs) induced by direct ionization from heavy-ion tracks in an IC. The qualitative charge transport has been simulated using a two-dimensional numerical code in cylindrical coordinates. The experimental bit-map data clearly show the manifestation of lateral charge transport in the creation of adjacent multiple-bit errors from a single heavy-ion track. The heavy-ion data further demonstrate the occurrence of multiple-bit errors from single ion tracks with sufficient stopping power. The qualitative numerical simulation results suggest that electric-field-funnel-aided (drift) collection accounts for single error generated by an ion passing through a charge-collecting junction, while multiple errors from a single ion track are due to lateral diffusion of ion-generated charge.
Zoutendyk, J. A.↗
Analysis and characterizations of planar transmission structures and components for superconducting and monolithic integrated circuits
The analysis and modeling of superconducting planar transmission lines were performed. Theoretically, the highest possible Q values of superconducting microstrip line was calculated and, as a result, it provided the Q value that the experiment can aim for. As an effort to search for a proper superconducting transmission line structure, the superconducting microstrip line and coplanar waveguide were compared in terms of loss characteristics and their design aspects. Also, the research was expanded to a superconducting coplanar waveguide family in the microwave packaging environment. Theoretically, it was pointed out that the substrate loss is critical in the superconducting transmission line structures.
Itoh, Tatsuo↗
Simplified calculation of wave-coupling between lines in high-speed integrated circuits
The construction of time-domain solutions by the superposition of modes is explained for the general case, which may not have any symmetry in the lines or terminations. This simplified method requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of the actual logic gates. Several examples of results of crosstalk calculations made by the simplified method are presented and compared with corresponding results obtained using the SPICE transmission-line methods of Tripathi and Rettig (1985) along with full SPICE models of the logic gates. The simplified approach is shown to give satisfactory agreement for most purposes.
Matthaei, George L.↗
Healing of voids in the aluminum metallization of integrated circuit chips
The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.
Cuddihy, Edward F.↗